K. Mai, R. Ho, E. Alon, L. Dean, Younggon Kim, P. Dinesh, M. Horowitz
{"title":"Architecture and circuit techniques for a reconfigurable memory block","authors":"K. Mai, R. Ho, E. Alon, L. Dean, Younggon Kim, P. Dinesh, M. Horowitz","doi":"10.1109/ISSCC.2004.1332813","DOIUrl":null,"url":null,"abstract":"A 2 kB reconfigurable SRAM block, using self-timed, pulse-mode circuits capable of emulating a portion of a cache or a streaming FIFO is realized in a 1.8 V 0.18 /spl mu/m CMOS process and operates at 1.1 GHz (10F04 cycle). The additional logic needed for reconfigurability consumes 26% of the total power and 32% of the total area.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332813","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18
Abstract
A 2 kB reconfigurable SRAM block, using self-timed, pulse-mode circuits capable of emulating a portion of a cache or a streaming FIFO is realized in a 1.8 V 0.18 /spl mu/m CMOS process and operates at 1.1 GHz (10F04 cycle). The additional logic needed for reconfigurability consumes 26% of the total power and 32% of the total area.
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