Components of a 12-bit 50 Ms/s non-radix 2 pipeline analog-to-digital converter

Abstract

The design and implementation of the components of a non-radix 2 12-bit pipeline analog-to-digital converter (ADC) is presented in this paper. The ADC is composed of 13 pipeline stages each with a gain of 1.9 rather than the traditional 2. Each stage of the pipeline is composed of a fully differential sample and hold amplifier (SHA), a 1-bit sub-ADC and a 1-bit sub-DAC. The sub-DAC functionality is rolled in as part of the SHA switched-capacitor circuit, which is referred to as the multiplying DAC (MDAC). The ADC has been implemented in a 0.35 /spl mu/m single-poly CMOS digital process.