A computational study of PCB layer orientation of WCSP assembly under temperature dependent drop impact loading

Abstract

Chip Scale Packages (CSP) are used more and more in the portable electronic devices with its growing popularity due to small form factor. Electrical, Thermomechanical and Mechanical loadings act simultaneously on the electronic products during their daily usage. Due to the market demand, new high-performance functions are continuously being integrated with these devices despite the decreasing from factor and generation of more thermal stresses inside. These smaller devices are more prone to accidental drop and experience impact load, causing board interconnect failure by the repeatability of the drop occurrences. Therefore, the reliability of these products due to various loadings are being researched by taking multi-dimensional approach. A computational study has been carried out in this paper to investigate the effect of impact loading on the solder joints of WLCSP component boards. Here, a more thorough understanding of the solder joint behavior is examined by carrying out drop test with respect to elevated temperature and using PCBs of varying thickness and layer stack-ups. The same WLCSP is used for different boards and subjected to drop test according to the JEDEC specifications [1]. Two different types of boards are used and to simulate the actual drop test modified Input G method, that is Direct Acceleration Input method, was followed. The comparison of the boards has been made to understand the effect of temperature on the reliability of solder interconnects and on the strain generation induced in the PCBs during the drop test. It has been found that due to decreasing elastic modulus at higher temperature the behavior of both the boards are similar except the fact that thin board experiences relatively more stress in its interconnects after crossing a threshold temperature.