Input-specific Dynamic Power Optimization for VLSI Circuits

Fei Hu, V. Agrawal
{"title":"Input-specific Dynamic Power Optimization for VLSI Circuits","authors":"Fei Hu, V. Agrawal","doi":"10.1145/1165573.1165630","DOIUrl":null,"url":null,"abstract":"Literature proposes linear programming (LP) methods for glitch-less design of digital circuits. Considering the worst-case these methods ensure absence of glitches for any arbitrary state of primary input as well as internal signals. In this paper, we examine an unexplored aspect, i.e., glitch-free design with respect to a specific set of vectors (patterns). Introducing the logic-level concepts of glitch-generation patterns and glitch-generation probability, which are analyzable through logic simulation, we remove glitch filtering requirements from gates on which the given set of input vectors cannot produce glitches. We relax constraints of any existing LP either selectively or probabilistically. Such input-specific design from an LP model without process variation and another with process variation reduced the number of delay buffer overhead by up to 80% and 63%, respectively, while maintaining the power reduction and overall delay","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"43 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1165573.1165630","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

Abstract

Literature proposes linear programming (LP) methods for glitch-less design of digital circuits. Considering the worst-case these methods ensure absence of glitches for any arbitrary state of primary input as well as internal signals. In this paper, we examine an unexplored aspect, i.e., glitch-free design with respect to a specific set of vectors (patterns). Introducing the logic-level concepts of glitch-generation patterns and glitch-generation probability, which are analyzable through logic simulation, we remove glitch filtering requirements from gates on which the given set of input vectors cannot produce glitches. We relax constraints of any existing LP either selectively or probabilistically. Such input-specific design from an LP model without process variation and another with process variation reduced the number of delay buffer overhead by up to 80% and 63%, respectively, while maintaining the power reduction and overall delay
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
VLSI电路输入特定动态功率优化
文献提出线性规划(LP)方法用于数字电路的无故障设计。考虑到最坏情况,这些方法保证了在任意的主输入和内部信号状态下都不会出现故障。在本文中,我们研究了一个未探索的方面,即关于一组特定向量(模式)的无故障设计。引入故障产生模式和故障产生概率的逻辑级概念,通过逻辑仿真分析,消除了给定输入向量集合上不能产生故障的门的故障滤波要求。我们有选择地或概率地放宽任何现有LP的约束。这种来自无进程变化的LP模型和有进程变化的LP模型的特定输入设计分别将延迟缓冲开销的数量减少了80%和63%,同时保持了功耗降低和总体延迟
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A Novel Dynamic Power Cutoff Technique (DPCT) for Active Leakage Reduction in Deep Submicron CMOS Circuits Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers Power Reduction in an H.264 Encoder Through Algorithmic and Logic Transformations An Efficient Chip-level Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction Energy-efficient Motion Estimation using Error-Tolerance
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1