Accelerating program execution using hybrid control flow and dataflow architectures

Abstract

Computer architectures based on control flow type of processors suffer from the problem of memory bandwidth becoming a bottleneck. Accelerating program execution relies mostly on spreading the work over processing units. This imposes the necessity for communication between these units. Dataflow architectures solve the computation problem by treating the execution as a factory, where many operations are done in parallel. However, the constraint is that only the program for which the dataflow hardware is constructed could be executed. Reconfigurable dataflow hardware solves this problem at the price of having to reconfigure the hardware whenever a new program should be executed. Also, this reduces efficiency. Hybrid control flow and dataflow architectures are capable of executing both programs written for dataflow and for control flow architectures. Based on the hybrid architectures, a greedy algorithm is presented that schedules programs for dataflow and control flow processors.