Prototyping the DLX microprocessor

[1992 Proceedings] The Third International Workshop on Rapid System Prototyping Pub Date : 1992-06-23 DOI:10.1109/IWRSP.1992.243912

B. Fagin, Pichet Chintrakulchai

引用次数: 6

Abstract

The prototyping of a functioning DLX microprocessor, based on the 32-b instruction set architecture developed by D. Patterson and J. Hennessy (in Computer Architecture: A Quantitative Approach, 1990), is described. This architecture is an emerging academic standard but has yet to be successfully prototyped. An implementation of DLX as a 12-in*15-in two-layer circuit board, containing 59 chips and running on a 2-MHz clock, is described. The execution of DLX programs and the problems encountered are discussed.<>

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DLX微处理器原型

描述了基于D. Patterson和J. Hennessy(《计算机体系结构:定量方法》，1990)开发的32b指令集体系结构的功能DLX微处理器的原型。这种架构是一种新兴的学术标准，但尚未成功实现原型。描述了DLX作为一个12英寸*15英寸的两层电路板的实现，包含59个芯片，在2 mhz时钟上运行。讨论了DLX程序的执行和遇到的问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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[1992 Proceedings] The Third International Workshop on Rapid System Prototyping

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