1.5um CMOS gate arrays with analog/digital macros designed using the common base arrays

Abstract

Mixed analog and digital circuits are realized on a single chip of 1.5um rule, single t5V power supplied, si.licon gate, and 320 through 19600 cells CMOS digital gate arrays without any extension of turn-around time and any restriction of designing. Voltage comparator with input offset voltage of lOmV MAX. and response time of 60nsec. D/A converters and A/D converters with 4 bit, 6 bit, 8 bit respectively, and an analog switch with 250hm on-resistance can exist simultaneously with digital circuits. Using this technology, about 1/10 of turnaround time on system developments compared with full-custom LSIs can be achieved. INTRODUCTION I t is desired eagerly in the semi-custom LSI field to integrate a system on a single chip by establishing a mixture of analog and digital technologies. Up to this time, there are a few ways to create mixed analog and digital circuits; i.e., full-custom LSIs, standard cells, masterslice LSIs which have more than 2 channel length transistors for analog circuit parts and digital circuit parts. or gate array of which all base transistor arrays are long channel length type [ I ] , t21. Each of them have several weak points, for example long turn-around time, high development Cost, restriction of the ratio between analog circuit parts and digital circuit parts, very Poor digital circuit's performance, and so on. STRUCTURES Analog function blocks are produced on base transistor arrays of commonly used 1.5um rule, single +5V power.supplied, and silicon gate CMOS digital gate array series. This gate array series contains 16 masters with 320 through 19600 cells. Figure 1 shows a microphotograph of a chip including analog function blocks. All of analog circuits can be placed anywhere on the base transistor arrays with only a few consideration (ex. cross talk. noise etc.) like digital circuits. These analog function blocks are registered as hardware macros in function block libraries. PRODUCTS DEVELOPMENT FLOW Gate arrays including analog circuits are developed according to the flow chart shown in Figure 2 . Just the same development flow and CAD tools of designing gate arrays with only digital circuits are used. In case of circuit simulation, analog function blocks are treated as black boxes. And only connections between analog function blocks and other blocks are checked. In this way, the turn-around time from the end o f the circuit simulation to the supply of engineering sample of mixed analog and digital circuits is reduced to about 1/10 compared with fullcustom LSIs. VOLTAGE COUPARAT ORS short channel length unit transistors such as: Wp/Lp = 33um/1.8um All analog circuits are constructed with WN/LN = 33um/1.6um, Figure 3 shows one of the comparator's layout pattern. Input transistors of differential Stage uses two unit transistors each, and they are placed cross coupled with each other. And power supply wires are also placed equally for the input pair transistors. The comparator's layout is made under such consideration, as a result, an input offset voltage is within g 0 m V MAX., and a response time is 60nsec TYP.. The distribution of comparator's input Offset voltage is shown in Figure 4 .