Single-instruction based programmable memory BIST for testing embedded DRAM

Abstract

With the increasing functionalities in modern SoC design, the need for dense embedded memory is growing. The test issue for this high density embedded DRAM (eDRAM) macro in a complex integration environment is becoming an important issue. In this work, we propose a single-instruction based programmable memory BIST for testing an eDRAM macro. Based on our BIST design, the supported memory testing algorithms are classified into five groups. Moreover, a compact instruction is proposed to encode the operation of each group and a two-level address generator is adopted to produce all the required addressing indexes. The proposed architecture provides a better design tradeoff in terms of the area overhead and the programmability compared with the existing work.