FPGA-Driven DAC with Second Order Sliding Mode Control of Filter Model for Hardware-In-the-Loop Simulators

Abstract

The advances in FPGA technology have enabled to develop fast HIL (Hardware-in-the-Loop) simulators, revolutionizing control software and hardware development for power electronics. HIL simulators should reproduce the same analogue signals that could be measured on real main circuits. A very common limitation in these applications is the usable pin count of the FPGA, therefore using the most pin-effective Digital-to-Analogue Converters (DACs) becomes critical. $\Sigma-\Delta$ DACs provide a simple, FPGA-synthesizable solution using a single pin for each output, but the output signal's bandwidth and latency is usually not sufficient, because of the required analogue filters. Higher order $\Sigma-\Delta$ DACs usually perform much better in the aspect of the Signal-to-Noise-Ratio (SNR) but not the usable bandwidth. This paper introduces a new bitstream DAC architecture based on the sliding mode control of the output analogue filter model. It is optimized mainly to reproduce current transducer signals in power electronics (usually triangle waves), which can be done more accurately than traditional $\Sigma-\Delta$ solutions.