G. Piccinni, G. Avitabile, G. Coviello, C. Talarico
{"title":"Implementation of a Real-Time Distance Evaluation Algorithm for Wireless Localization Systems","authors":"G. Piccinni, G. Avitabile, G. Coviello, C. Talarico","doi":"10.1109/MWSCAS.2019.8884966","DOIUrl":null,"url":null,"abstract":"Abstract-The paper describes the FPGA implementation of a novel TDOA distance evaluation algorithm that combine the characteristics of an OFDM symbol with the properties of the Zadoff-Chu mathematical sequences. The distance evaluation system has been validated in presence of severe multipath interference and allows to achieve an accuracy that is always within 1.2cm of the target position. The algorithm is implemented using the FPGA (Cyclone IV-E EP4CE115F29C8L Cyclone IV-E) available on the Altera’s DE2-115 development board. The implementation requires about 120k bit of memory and less than 40k logic elements (of which about 30k are registers).","PeriodicalId":287815,"journal":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2019.8884966","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Abstract-The paper describes the FPGA implementation of a novel TDOA distance evaluation algorithm that combine the characteristics of an OFDM symbol with the properties of the Zadoff-Chu mathematical sequences. The distance evaluation system has been validated in presence of severe multipath interference and allows to achieve an accuracy that is always within 1.2cm of the target position. The algorithm is implemented using the FPGA (Cyclone IV-E EP4CE115F29C8L Cyclone IV-E) available on the Altera’s DE2-115 development board. The implementation requires about 120k bit of memory and less than 40k logic elements (of which about 30k are registers).
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
