T. Hashimoto, F. Sato, T. Aoyama, H. Suzuki, H. Yoshida, H. Fujii, T. Yamazaki
{"title":"A 73 GHz f/sub T/ 0.18 /spl mu/m RF-SiGe BiCMOS technology considering thermal budget trade-off and with reduced boron-spike effect on HBT characteristics","authors":"T. Hashimoto, F. Sato, T. Aoyama, H. Suzuki, H. Yoshida, H. Fujii, T. Yamazaki","doi":"10.1109/IEDM.2000.904280","DOIUrl":null,"url":null,"abstract":"This paper describes a 73 GHz f/sub T/ 0.18 /spl mu/m SiGe BiCMOS technology. This BiCMOS technology has the following key points: (1) The 2-step annealing technique for CMOS is utilized to solve the thermal budget trade-off between SiGe HBTs and CMOS. (2) A robust Ge profile design is implemented to improve the thermal stability of the SiGe base layer. (3) The Si-spacer layer is inserted between the Si collector and the SiGe base layer in order to reduce undesirable boron-spike effect. This process yields the SiGe HBT with f/sub T/ of 73 GHz and f/sub max/ of 61 GHz without compromising 0.18 /spl mu/m p/sup +//n/sup +/ dual gate CMOS characteristics.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2000.904280","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
This paper describes a 73 GHz f/sub T/ 0.18 /spl mu/m SiGe BiCMOS technology. This BiCMOS technology has the following key points: (1) The 2-step annealing technique for CMOS is utilized to solve the thermal budget trade-off between SiGe HBTs and CMOS. (2) A robust Ge profile design is implemented to improve the thermal stability of the SiGe base layer. (3) The Si-spacer layer is inserted between the Si collector and the SiGe base layer in order to reduce undesirable boron-spike effect. This process yields the SiGe HBT with f/sub T/ of 73 GHz and f/sub max/ of 61 GHz without compromising 0.18 /spl mu/m p/sup +//n/sup +/ dual gate CMOS characteristics.