P. Camino, D. Dallet, B. Quertier, A. Baudry, G. Comoretto, B. Le Gal
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引用次数: 0
Abstract
This study was initiated in the frame of the 2-stage, 32-demultiplexed input digital filter of the large correlator system of the ALMA (Atacama Large Millimeter Array) interferometer project. The main goal of this work was to reduce the power consumption of the implemented architecture in large FPGAs by optimizing the amount of logic elements. A modified structure of the CIC (cascaded integrator comb) filter for a time demultiplexed architecture is investigated. Different implementations are discussed and compared in terms of performances (complexity, power consumption). We demonstrate that a multistage architecture significantly improves the power dissipation.
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