A tool to generate models based on behavioral IBIS models

B. S. Deepaksubramanyan, C. Chen, A. Nunez
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引用次数: 3

Abstract

Input/Output Buffer Information Specification (IBIS) behavioral models are widely used for circuit-level signal integrity (SI) analysis due to its fast simulation speed and good accuracy. This work presents a tool to generate models of circuits specified by IBIS models. The model generation tool estimates poles, rise time and fall time of a circuit specified by IBIS models. The method consists of two steps; first regression analysis is performed on IBIS data with Weibull distribution function (WCDF) as the regression function. Based on the estimated parameter values, rise time and fall time values are obtained. The second step involves matching moments of WCDF to circuit moments and obtaining the estimated poles of the system. The method is generic and is scalable in nanometer CMOS. CMOS inverters have been used to demonstrate the methodology.
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生成基于行为IBIS模型的模型的工具
输入/输出缓冲信息规范(IBIS)行为模型以其快速的仿真速度和良好的精度被广泛应用于电路级信号完整性分析。这项工作提出了一种工具来生成由IBIS模型指定的电路模型。模型生成工具估计由IBIS模型指定的电路的极点、上升时间和下降时间。该方法包括两个步骤;首先以威布尔分布函数(WCDF)作为回归函数对IBIS数据进行回归分析。根据估计的参数值,得到上升时间和下降时间的值。第二步是将WCDF的矩与电路的矩进行匹配,得到系统的估计极点。该方法具有通用性,在纳米CMOS中具有可扩展性。CMOS逆变器已被用来证明该方法。
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