Selecting appropriate calibration points for an ultra low area 8-bit subrange ADC

N. Petrellis, M. Birbas, J. Kikidis, A. Birbas
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引用次数: 1

Abstract

An ultra low area 8-bit subrange Analogue/Digital Converter that consists of a pair of Flash 4-bit converter stages is described in this paper emphasising on the appropriate method for its real time calibration. Its active area occupies only 0.04 mm2 and dissipates less than 22 mW. The sampling rate is higher than 500 MS/s and the achieved Signal to Noise and Distortion Ratio is higher than 40 dB. A voltage mode integer divider is used at the input of this Analogue/Digital Converter driving the two output Flash stages by its quotient and residue. The ultra low area and power is owed to the use of the integer divider at the input stage of the subrange converter and the employment of a “thermometer to binary encoder” instead of a full 4-bit Flash Analogue/Digital Converter for the generation of the 4 most significant bits. The calibration method employed for this Analogue/Digital Converter is based on the proper biasing of the resistor ladders used by the fine 4-bit Flash stage as well as on properly delaying and shifting of the divider signals that generate the residue.
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为超低面积8位子范围ADC选择合适的校准点
本文介绍了一种由一对Flash 4位转换器级组成的超低面积8位子范围模拟/数字转换器,重点介绍了其实时校准的适当方法。其有效面积仅为0.04 mm2,耗散功率小于22 mW。采样率大于500ms /s,实现的信噪比和失真比大于40db。在模拟/数字转换器的输入端使用电压型整数分频器,通过其商和余驱动两个输出Flash级。超低的面积和功率是由于在子范围转换器的输入阶段使用整数分频器和使用“温度计到二进制编码器”而不是一个完整的4位Flash模拟/数字转换器来生成4个最重要的位。该模拟/数字转换器采用的校准方法是基于精细4位Flash级使用的电阻阶梯的适当偏置以及产生剩余的分频信号的适当延迟和移位。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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