Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548431
Björn Andersson, Nuno Pereira, E. Tovar, F. Pacheco
Database query languages on relations (for example SQL) make it possible to join two relations. This operation is very common in desktop/server database systems but unfortunately query processing systems in networked embedded computer systems currently do not support this operation; specifically, the query processing systems TAG, TinyDB, Cougar do not support this. We show how a prioritized medium access control (MAC) protocol can be used to efficiently execute the database operation join for networked embedded computer systems where all computer nodes are in a single broadcast domain.
{"title":"Using a prioritized MAC protocol to execute the database operation join in networked embedded computer systems","authors":"Björn Andersson, Nuno Pereira, E. Tovar, F. Pacheco","doi":"10.1109/WISES.2010.5548431","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548431","url":null,"abstract":"Database query languages on relations (for example SQL) make it possible to join two relations. This operation is very common in desktop/server database systems but unfortunately query processing systems in networked embedded computer systems currently do not support this operation; specifically, the query processing systems TAG, TinyDB, Cougar do not support this. We show how a prioritized medium access control (MAC) protocol can be used to efficiently execute the database operation join for networked embedded computer systems where all computer nodes are in a single broadcast domain.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"277 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120840320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548424
Michael Schorer, Stefan Kuntz, J. Mottok
The advantages of component-based systems include reuse of generic components as well as adaption through variants. However, they bare a high risk of containing incompatibilities between components, due to the lack of control over the integration-relevant aspects of their components. Current development processes are able to detect incompatibilities between components only at very late stages of system development. The Virtual Integration methodology is an approach to detect and to solve compatibility issues during early stages of system design. The methodology supports developers with a set of measures to reduce the risk of incompatibilities to a minimum at each abstraction layer of their system architecture. Realtime requirements of embedded systems make it necessary to support the methodology with a formal model, which can describe dynamic properties of these systems. In our approach, we use interface automata because they offer a lightweight formalism to describe the behavior of components and to verify their compatibility based on these descriptions. In a feasibility study we show, to which extend interface automata are adequate for the foresaid purpose in the automotive application field.
{"title":"Verification of behavioral compatibility in the Virtual Integration methodology","authors":"Michael Schorer, Stefan Kuntz, J. Mottok","doi":"10.1109/WISES.2010.5548424","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548424","url":null,"abstract":"The advantages of component-based systems include reuse of generic components as well as adaption through variants. However, they bare a high risk of containing incompatibilities between components, due to the lack of control over the integration-relevant aspects of their components. Current development processes are able to detect incompatibilities between components only at very late stages of system development. The Virtual Integration methodology is an approach to detect and to solve compatibility issues during early stages of system design. The methodology supports developers with a set of measures to reduce the risk of incompatibilities to a minimum at each abstraction layer of their system architecture. Realtime requirements of embedded systems make it necessary to support the methodology with a formal model, which can describe dynamic properties of these systems. In our approach, we use interface automata because they offer a lightweight formalism to describe the behavior of components and to verify their compatibility based on these descriptions. In a feasibility study we show, to which extend interface automata are adequate for the foresaid purpose in the automotive application field.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129303940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548422
F. D. Franco, C. Tachtatzis, B. Graham, M. Bykowski, D. Tracey, N. Timmons, J. Morrison
The emerging area of body area networks (BAN) imposes challenging requirements on hardware and software to achieve the desired lifetimes for certain devices such as long term medical implants. In this paper, we propose a novel approach to the measurement and characterisation of the energy consumption of BAN devices. The approach uses a low cost energy auditing circuit and addresses the problem of accurately measuring low-level current consumption. This new technique will allow precise and analytical measurements of systems and components in terms of energy. This will help circuit designers minimise power consumption in BAN devices. Software engineers might use this approach to validate and optimise embedded code. Network engineers can optimise network parameters to reduce the power consumption of a single node. Adoption of the proposed technique will aid the development of ultra-low power wireless BANs. Results are presented on current characterisation for two wireless motes.
{"title":"Current characterisation for ultra low power wireless body area networks","authors":"F. D. Franco, C. Tachtatzis, B. Graham, M. Bykowski, D. Tracey, N. Timmons, J. Morrison","doi":"10.1109/WISES.2010.5548422","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548422","url":null,"abstract":"The emerging area of body area networks (BAN) imposes challenging requirements on hardware and software to achieve the desired lifetimes for certain devices such as long term medical implants. In this paper, we propose a novel approach to the measurement and characterisation of the energy consumption of BAN devices. The approach uses a low cost energy auditing circuit and addresses the problem of accurately measuring low-level current consumption. This new technique will allow precise and analytical measurements of systems and components in terms of energy. This will help circuit designers minimise power consumption in BAN devices. Software engineers might use this approach to validate and optimise embedded code. Network engineers can optimise network parameters to reduce the power consumption of a single node. Adoption of the proposed technique will aid the development of ultra-low power wireless BANs. Results are presented on current characterisation for two wireless motes.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548437
M. Shariat, Nima Azizibabani
One of the most significant concerns in designing on-chip networks is guaranteeing QoS requirements for various applications. In this paper, we propose a buffering method which reduces the router's area and in turn network cost without affecting the QoS issues. The proposed method rather than considering a dedicated buffer for each class of traffic, assigns a single shared buffer on each port to the all existing prioritized traffic classes. Simulation results show that exploiting shared buffer increases buffer utilization. Moreover, the required space of the shared buffer is 37.5% less than the space needed for the dedicated buffers. Furthermore, a controller is developed to both manage the shared buffer and allocate a particular amount of the shared buffer as an upper limit to each class of traffic; accordingly, QoS requirements will be preserved for high prioritized traffic classes.
{"title":"Reducing router's area in NoC by changing buffering method while providing QoS","authors":"M. Shariat, Nima Azizibabani","doi":"10.1109/WISES.2010.5548437","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548437","url":null,"abstract":"One of the most significant concerns in designing on-chip networks is guaranteeing QoS requirements for various applications. In this paper, we propose a buffering method which reduces the router's area and in turn network cost without affecting the QoS issues. The proposed method rather than considering a dedicated buffer for each class of traffic, assigns a single shared buffer on each port to the all existing prioritized traffic classes. Simulation results show that exploiting shared buffer increases buffer utilization. Moreover, the required space of the shared buffer is 37.5% less than the space needed for the dedicated buffers. Furthermore, a controller is developed to both manage the shared buffer and allocate a particular amount of the shared buffer as an upper limit to each class of traffic; accordingly, QoS requirements will be preserved for high prioritized traffic classes.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132903009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548433
G. Cardarilli, L. Nunzio, R. Fazzolari, M. Re
Advanced bit manipulation operations are not efficiently supported by standard microprocessors since they are optimized for fixed data size operations. In literature several hardware solutions are proposed to overcome this problem [1], [3] and [4]. In this work we present the experimental results of a new architecture based on LEON-2 and a simplified version of ADAPTO [1] (Adder-based Dynamic Architecture for Processing Tailored Operators), acting as a co-processor. For our experiments we run a set of Bit Manipulation Algorithms on the LEON-2 processor in presence and absence of the ADAPTO unit. This permits to measure the speed-up factor obtained using the proposed reconfigurable co-processor.
{"title":"Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit","authors":"G. Cardarilli, L. Nunzio, R. Fazzolari, M. Re","doi":"10.1109/WISES.2010.5548433","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548433","url":null,"abstract":"Advanced bit manipulation operations are not efficiently supported by standard microprocessors since they are optimized for fixed data size operations. In literature several hardware solutions are proposed to overcome this problem [1], [3] and [4]. In this work we present the experimental results of a new architecture based on LEON-2 and a simplified version of ADAPTO [1] (Adder-based Dynamic Architecture for Processing Tailored Operators), acting as a co-processor. For our experiments we run a set of Bit Manipulation Algorithms on the LEON-2 processor in presence and absence of the ADAPTO unit. This permits to measure the speed-up factor obtained using the proposed reconfigurable co-processor.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123865848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548434
R. d'Aparo, Giorgio Crostella, Davide Nicoletti, S. Orcioni, M. Conti
Recently great effort has been done in the development of high efficient DC-AC switching power converters for renewable energies and in particular for solar cells. The common algorithm used to control DC-AC switching power converters is Pulse Width Modulation. The present work presents the use of Sigma-Delta modulators for the control of the switches of DC-AC switching power converters. The proposed control algorithm presents the advantage of a reduction of conducted electromagnetic interferences with respect to Pulse Width Modulation. A DC-AC switching power converter has been simulated using SystemC-WMS and a prototype has been implemented.
{"title":"DC-AC power converter using sigma-delta modulation","authors":"R. d'Aparo, Giorgio Crostella, Davide Nicoletti, S. Orcioni, M. Conti","doi":"10.1109/WISES.2010.5548434","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548434","url":null,"abstract":"Recently great effort has been done in the development of high efficient DC-AC switching power converters for renewable energies and in particular for solar cells. The common algorithm used to control DC-AC switching power converters is Pulse Width Modulation. The present work presents the use of Sigma-Delta modulators for the control of the switches of DC-AC switching power converters. The proposed control algorithm presents the advantage of a reduction of conducted electromagnetic interferences with respect to Pulse Width Modulation. A DC-AC switching power converter has been simulated using SystemC-WMS and a prototype has been implemented.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115700783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548436
Constantinos Stefanatos, I. Papaefstathiou, C. Manifavas
Network Processors are used at the core of the Internet, providing routers, switches and other essential network devices with the necessary processing power to deliver proper data forwarding and other network related functions (VoIP, security, etc.) at the required level of performance. In this paper, we present a Network Processor architecture, designed to support all the fundamental instructions needed to deliver proper frame processing. It is designed and implemented on a specific FPGA board, employing Xilinx's Virtex-5, in order to allow for rapid deployment and usage. Apart from the architecture's description, performance measurements are provided that demonstrate the architecture's capabilities.
{"title":"Development and implementation of a Network Processor Architecture in reconfigurable logic (FPGA)","authors":"Constantinos Stefanatos, I. Papaefstathiou, C. Manifavas","doi":"10.1109/WISES.2010.5548436","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548436","url":null,"abstract":"Network Processors are used at the core of the Internet, providing routers, switches and other essential network devices with the necessary processing power to deliver proper data forwarding and other network related functions (VoIP, security, etc.) at the required level of performance. In this paper, we present a Network Processor architecture, designed to support all the fundamental instructions needed to deliver proper frame processing. It is designed and implemented on a specific FPGA board, employing Xilinx's Virtex-5, in order to allow for rapid deployment and usage. Apart from the architecture's description, performance measurements are provided that demonstrate the architecture's capabilities.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114092497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548427
M. Steindl, J. Mottok, H. Meier
Embedded real-time systems are often used in harsh environments, for example engine control systems in automotive vehicles. In such ECUs (Engine Control Unit) faults can lead to serious accidents. In this paper we propose a safety embedded architecture based on coded processing. This framework only needs two channels to provide fault tolerance and allows the detection and identification of permanent and transient faults. Once a fault is detected by an observer unit the SES guard makes it visible and initiates a suitable failure reaction.
{"title":"SES-based framework for fault-tolerant systems","authors":"M. Steindl, J. Mottok, H. Meier","doi":"10.1109/WISES.2010.5548427","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548427","url":null,"abstract":"Embedded real-time systems are often used in harsh environments, for example engine control systems in automotive vehicles. In such ECUs (Engine Control Unit) faults can lead to serious accidents. In this paper we propose a safety embedded architecture based on coded processing. This framework only needs two channels to provide fault tolerance and allows the detection and identification of permanent and transient faults. Once a fault is detected by an observer unit the SES guard makes it visible and initiates a suitable failure reaction.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126390601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548430
Jesús Sáez Gómez-Escalonilla, Julio Ángel Cano Romero, N. M. Madrid, R. Seepold
Home networks comprise very heterogeneous devices interconnected through the residential gateway. They deploy complex services networks within the home environment using technologies such as Universal Plug and Play (UPnP). This technology provides the home network clients with a standard for device auto-discovery and transparent interoperability. However, the UPnP standard has an important constraint. It is designed to be used in local networks, so it is not suitable for service sharing among home networks. This article solves this limitation proposing a small footprint, low latency and non intrusive solution, capable of deploying a common UPnP services network between several residential environments. The proposed system consists of a software module installable over OSGi-based gateways, which applies identity theft and NAT techniques to allow the interoperation between UPnP devices from different subnets. It is based on SIP and UPnP IGD technologies, as well as on an extension of the UPnP standard fully described in this article. As a result, a prototype has been implemented, in order to check the successful operation of the complete system.
{"title":"A gateway-based solution for remote accessing to residential UPnP services networks","authors":"Jesús Sáez Gómez-Escalonilla, Julio Ángel Cano Romero, N. M. Madrid, R. Seepold","doi":"10.1109/WISES.2010.5548430","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548430","url":null,"abstract":"Home networks comprise very heterogeneous devices interconnected through the residential gateway. They deploy complex services networks within the home environment using technologies such as Universal Plug and Play (UPnP). This technology provides the home network clients with a standard for device auto-discovery and transparent interoperability. However, the UPnP standard has an important constraint. It is designed to be used in local networks, so it is not suitable for service sharing among home networks. This article solves this limitation proposing a small footprint, low latency and non intrusive solution, capable of deploying a common UPnP services network between several residential environments. The proposed system consists of a software module installable over OSGi-based gateways, which applies identity theft and NAT techniques to allow the interoperation between UPnP devices from different subnets. It is based on SIP and UPnP IGD technologies, as well as on an extension of the UPnP standard fully described in this article. As a result, a prototype has been implemented, in order to check the successful operation of the complete system.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123377159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548421
Aleksander Pruszkowski, T. Paczesny, J. Domaszewicz
The paper presents reusable techniques for building a runtime environment for a middleware targeted at heterogeneous sensor/actuator networks (SAN). The SAN is heterogeneous in that nodes differ as to the underlying MCU and OS platform, as well as sensor and actuator resources. Applications destined for the middleware are written in C and then transformed into executables interpreted by a virtual machine. The runtime residing on each node exposes, besides the virtual CPU, a node-independent set of general-purpose primitives and a node-specific set of primitives representing the node's sensors and actuators. The latter primitives are drawn from a potentially huge set of primitives representing all sensors and actuators possible in a given application domain. A proof-of-concept implementation of the runtime environment, for a severely resource-constrained platform, is presented.
{"title":"From C to VM-targeted executables: Techniques for heterogeneous sensor/actuator networks","authors":"Aleksander Pruszkowski, T. Paczesny, J. Domaszewicz","doi":"10.1109/WISES.2010.5548421","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548421","url":null,"abstract":"The paper presents reusable techniques for building a runtime environment for a middleware targeted at heterogeneous sensor/actuator networks (SAN). The SAN is heterogeneous in that nodes differ as to the underlying MCU and OS platform, as well as sensor and actuator resources. Applications destined for the middleware are written in C and then transformed into executables interpreted by a virtual machine. The runtime residing on each node exposes, besides the virtual CPU, a node-independent set of general-purpose primitives and a node-specific set of primitives representing the node's sensors and actuators. The latter primitives are drawn from a potentially huge set of primitives representing all sensors and actuators possible in a given application domain. A proof-of-concept implementation of the runtime environment, for a severely resource-constrained platform, is presented.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114968713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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