{"title":"A Study of Side-Channel Effects in Reliability-Enhancing Techniques","authors":"Jianwei Dai, Lei Wang","doi":"10.1109/DFT.2009.32","DOIUrl":null,"url":null,"abstract":"Reliability-enhancing techniques are critical for nanoscale integrated systems under the pressure of various physical non-idealities such as process variations and manufacturing defects. However, it is unclear how these techniques will affect the side-channel information leaked through hardware implementations. The related side-channel effects may have direct implications to the security requirement in a wide range of applications. In this paper, we investigate this new problem for trusted hardware design. Employing information-theoretic measures, the relationship between reliability enhancements and the induced side-channel effects is quantitatively evaluated. Simulation results on EDC/ECC schemes in memory circuits are presented to demonstrate the application of the proposed method.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2009.32","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
Reliability-enhancing techniques are critical for nanoscale integrated systems under the pressure of various physical non-idealities such as process variations and manufacturing defects. However, it is unclear how these techniques will affect the side-channel information leaked through hardware implementations. The related side-channel effects may have direct implications to the security requirement in a wide range of applications. In this paper, we investigate this new problem for trusted hardware design. Employing information-theoretic measures, the relationship between reliability enhancements and the induced side-channel effects is quantitatively evaluated. Simulation results on EDC/ECC schemes in memory circuits are presented to demonstrate the application of the proposed method.
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