Multiple Bit Error Detection and Correction in Memory

Abstract

Technology evolution provides ever increasing density of transistors in chips, lower power consumption and higher performance. In this environment the occurrence of multiple-bit upsets (MBUs) becomes a significant concern. Critical applications need high reliability, but traditional error mitigation techniques assume only the single error model, and only a few techniques to correct MBUs at algorithm level have been proposed. In this paper, a novel circuit level technique to detect and correct multiple errors in memory is proposed. Since it is implemented at circuit level, it is transparent to programmers. This technique is based in the Decimal Hamming coding and here it is compared to Reed Solomon coding at circuit level. Experimental results show that for memory words wider than 16 bits, the proposed technique is faster and imposes lower area overhead than optimized RS, while mitigating errors affecting up to 25% of the memory word.