Power saving techniques to improve efficiency of a parallel-connected negative DC-DC converter

K. Eguchi, S. Pongswatd, T. Thepmanee, K. Fujimoto, H. Sasaki
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Abstract

A parallel-connected negative DC-DC converter using power saving techniques has been proposed in this paper. Unlike conventional negative converters, the proposed converter consists of four negative heap converters connected in parallel, where the power switch is driven by non-overlapped four-phase pulses cyclically. In two of the four negative heap converters, a part of the electric charge in parasitic capacitances is reused in each clock cycle. For this reason, the proposed converter can reduce energy loss than the conventional converters. The validity of the proposed technique was confirmed by simulation program with integrated circuit emphasis (SPICE) simulations and theoretical analysis. When the output load is 1 kΩ, the proposed converter was able to improve power efficiency more than 11% compared to the conventional converter.
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提高并联负型DC-DC变换器效率的节电技术
本文提出了一种采用节电技术的并联负型DC-DC变换器。与传统的负变换器不同,该变换器由四个并联的负堆变换器组成,其中功率开关由非重叠的四相脉冲周期性驱动。在四个负堆变换器中的两个中,寄生电容中的一部分电荷在每个时钟周期中被重复使用。因此,所提出的变换器比传统的变换器能减少能量损失。通过集成电路重点(SPICE)仿真和理论分析,验证了该技术的有效性。当输出负载为1 kΩ时,与传统变换器相比,所提出的变换器能够提高11%以上的功率效率。
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