Optimizing Power and Improving Performance of 4-16 Hybrid-Logic Line Decoder using Power Gating Technique

Abstract

Recently, power gating technique is being adopted in many designs for minimizing power consumption (MTCMOS). This paper mounts new hybrid-logic circuit design for inverted 4–16 decoder invented using sleep transistor capable of lowering power dissipation and power-delay product(PDP). Two circuit designs are proposed here using DEC-14 topology and DEC-15 topology at supply voltage of 1V and 10MHz frequency. Also, pulse input is provided to sleep transistor for switching action at 10MHz frequency. Employing this technique, considerably reduces leakage power, benefitting circuit design by improvising its key parameters. Later, various simulations results are represented on 32nm technology showing brief comparison between distinct circuits.