A Low-Power CT Second-Order VCO-Based ΔΣADC for Audio Recording on Skywater 130-nm

Abstract

This paper presents a low-power, highly-digital Analog-to-Digital Converter (ADC) that aims to meet the requirements of audio recording and processing for Internet-of-Thing (IoT) System-on-Chips (SoCs). In this work, we propose an architecture applying the time-encoding technique and second-order noise shaping ΔΣ modulation. Our design is composed of highly-digital circuits optimized to reach high Signal-to-Noise and Distortion Ratio (SNDR) with low power consumption. The proposed architecture is verified by SPICE simulation. Our ADC obtains an SNDR of 80.7 dB-A, equivalent to 12.3 Effective Number Of Bits (ENOB) at the bandwidth of 24 kHz. This ADC consumes an average of 0.16 mW at the supply voltage of 1.8 V on Skywater 130-nm technology.