Design and measurement of a compact on-interposer passive equalizer for chip-to-chip high-speed differential signaling

Abstract

In this paper, a compact on-interposer passive equalizer for chip-to-chip high-speed differential signaling was proposed and experimentally verified. By using the parasitic resistance and inductance of the coil-shaped on-interposer metal line, the proposed on-interposer passive equalizer achieves not only the wide-band equalization but also the compact size. Moreover, the symmetric structure of the proposed equalizer maintains the balance between the differential signals. The remarkable performance of the proposed on-interposer passive equalizer for differential signaling was successfully verified by a frequency- and time-domain measurement of up to 10 Gbps.