Interconnect design for a 32 nm node technology

Abstract

When high speed integrated circuits technology scales down from one node to the other, ITRS suggests a reduction in sizes by a factor of around square of 2, and recommends 17% of improvement on performance. But the obtained gain on active devices is foiled by an increase of interconnect propagation delays and critical crosstalk levels in the Back End of Line (BEOL). This issue especially concerns interconnect of the intermediate metal level. Our works are focused on the impact on signal transmission delay along interconnects of decreasing the space and width. To avoid new industrial manufacturing constraints on cost and reliability, this study is performed without modifying process and materials used in the BEOL of CMOS 45 nm IC. We will study interconnects of 50 nm width, with a 50 nm space between lines in accordance with speed and crosstalk levels requirements of CMOS 32 nm BEOL. When it becomes hard to meet all requirements, it is shown that interconnect density constraints should be relaxed to enlarge the scope of application.