A 4.5 Megabit, 560MHz, 4.5 Gbyte/s High Bandwidth SRAM

Abstract

High performance microprocessors require large caches with very high bandwidth and low latency to attain maximum performance. However, as technology scales to smaller dimensions and lower operating voltages, continuous improvements in memory performance require more aggressive chip architectures. This work focuses on the design and implementation of a large, fully pipelined, synchronous SRAM intended to demonstrate techniques for the design of high performance caches. This particular design was also used to gather yield and performance data on a developing silicon technology, and so process-independent design was necessary. The part is fabricated on Intel’s 0.25 micron, 1.8V suppIy voltage CMOS technology, described in [I]. Maximum frequency at 1.8V, 25OC is 560MHz (1.79nS cycle). Ignoring the error correction bits, that yields a buss bandwidth of 4.48 GByteIsecond. The die size is 142mm2.