Doping engineering to enhance performance of a silicon carbide power device

R. Radhakrishnan, M. F. Macmillan, R. Woodin
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引用次数: 2

Abstract

The doping of the drift layer of a 1-D SiC power device is designed to vary in steps, instead of traditional constant doping, and we show an experimental reduction of the resistance of the drift region below that achieved with constant doping by 7.34%. Sensitivity of doping design to material properties affects the improvement in characteristics. Stepped epitaxial doping presented here permits shrinkage of ∼ 3% of the die in typical commercial devices between 600 V and 1700 V while keeping the same electrical characteristics. Higher number of doping steps approach the ideal of an accurately graded epitaxy, with a tradeoff between increasing performance gains and increasing process complexity.
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掺杂工程提高碳化硅功率器件的性能
1-D SiC功率器件漂移层的掺杂被设计成不同的步骤,而不是传统的恒定掺杂,我们发现在实验中,漂移区的电阻比恒定掺杂降低了7.34%。掺杂设计对材料性能的敏感性影响着材料特性的改善。在这里提出的阶梯外延掺杂允许在600 V和1700 V之间的典型商用器件中,在保持相同的电气特性的同时,芯片的收缩约3%。更高数量的掺杂步骤接近精确分级外延的理想,在不断增加的性能增益和不断增加的工艺复杂性之间进行权衡。
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