Mixed bus width architecture for low cost AES VLSI design

Abstract

With the increase of security problem, AES is widely used in a lot of secure systems. For some low data throughput applications, low cost design is more attractive than high speed design. In this paper, low cost hardware architecture for AES algorithm is proposed. Mixed bus width architecture is used to reduce hardware cost and shorten critical path. The experimental results show that the lowest hardware cost implementation of AES algorithm is 4678 gates. The corresponding frequency is 80 MHz and the throughput is 51 Mbps. This architecture is very suitable for mid-throughput, low power and low hardware cost systems such as mobile system.