Real time embedded system IPs protection using chaotic maps

Abstract

In this paper and for the first time, a novel chaotic maps algorithm is proposed to be used in hardware on-chip security for real-time embedded systems. The aim is to cipher the original program rom by changing the contents and the locations of the original data to ban extracting designs of secure IPs. As we know, many strong ciphers have been applied widely, such as DES, AES and RSA. But most of them cannot be directly used to encrypt real-time embedded systems because their encryption speed is not fast enough and they are computationally intensive. So, in this work we present a fast chaotic-based encryption algorithm which is suitable for real-time embedded systems in terms of performance, area and power efficiency. To illustrate the effectiveness of the proposed algorithm, numerical simulations are presented. Moreover, the proposed chaotic algorithm is implemented using RTL-design. The proposed encryption gives 64 bits of encrypted data per clock cycle. The hardware implementation results give a synthesis clock frequency of 400 MHz and a throughput of 3.2 Gbps while using low area. This makes the proposed algorithm suitable for embedded systems. The RTL implementation results match the Matlab simulation results. The strong structural complexity of our proposed algorithm makes it difficult to predict the key and make it able to resist exhaustive attack, statistical attack and differential attack. All these features show that our proposed algorithm is very suitable for hardware on-chip security for real-time embedded systems. An exhaustive cryptanalysis was completed, allowing us to conclude that the system is secure. Moreover, it is cost-effective solution.