Layered-ECC: A Class of Double Error Correcting Codes for High Density Memory Systems

Abstract

As memory technology scales, the demand for higher performance and reliable operation is increasing as well. For main memory, e.g., DRAM, a conventional single error correcting double error detecting (SEC-DED) code may not be sufficient. However, existing double error correcting (DEC) codes either have very high decoder latency or high data redundancy. For flash-based memories, e.g., NAND flash, using a highly complex decoding scheme with a large number of clock cycles for the whole procedure creates a performance bottleneck. In this paper, a layered DEC code is proposed with a simple decoding procedure. The codes are shown to strike a good balance between redundancy and decoder complexity. A general construction methodology is presented. Two different decoding schemes can be implemented using the proposed methodology. One is a low latency decoding scheme that is useful for main memories which need high speed decoding for optimal performance. This scheme is shown to achieve better redundancy compared to existing low-latency codes as well as faster decoder latency compared to existing low-redundancy codes. The second decoding scheme is a low complexity decoding scheme which is useful for flash-based memories. This scheme is shown to have considerably less area compared to existing schemes. Also, it is shown that the proposed serial low complexity decoding scheme can take significantly fewer cycles to complete the whole decoding procedure; thus, enabling better performance compared to existing serial decoding schemes.