Pub Date : 2019-04-23DOI: 10.1109/VTS.2019.8758641
Jianwei Zhang, S. Gupta, William G. J. Halfond
Test generation for digital hardware is highly automated, scalable (in practice), and provides high test quality. In contrast, current software automatic test data generation approaches suffer from low test quality or high complexity. While mutation-oriented constraint-based test data generation for software was proposed to generate high quality test data for real program bugs, all existing approaches require symbolic analysis for the whole program, and hence are not scalable even for unit testing, i.e., testing the lowest-level software modules. We propose a new method inspired by hardware D-algorithm and divide and conquer for software test data generation. To reduce runtime complexity and improve scalability, we combine global structural analysis and a sequence of small reusable symbolic analyses of parts of the program, instead of symbolically executing each mutated version of the entire program. We also propose a multi-pass test generation system to further reduce runtime complexity and compact test data. We compare our tools with one of the best software test generation tools (EvoSuite[20], which won the SBST 2017 tool competition) and demonstrate that our approach generates higher quality unit tests in a scalable manner and provides a compact set of tests.
{"title":"A New Method for Software Test Data Generation Inspired by D-algorithm","authors":"Jianwei Zhang, S. Gupta, William G. J. Halfond","doi":"10.1109/VTS.2019.8758641","DOIUrl":"https://doi.org/10.1109/VTS.2019.8758641","url":null,"abstract":"Test generation for digital hardware is highly automated, scalable (in practice), and provides high test quality. In contrast, current software automatic test data generation approaches suffer from low test quality or high complexity. While mutation-oriented constraint-based test data generation for software was proposed to generate high quality test data for real program bugs, all existing approaches require symbolic analysis for the whole program, and hence are not scalable even for unit testing, i.e., testing the lowest-level software modules. We propose a new method inspired by hardware D-algorithm and divide and conquer for software test data generation. To reduce runtime complexity and improve scalability, we combine global structural analysis and a sequence of small reusable symbolic analyses of parts of the program, instead of symbolically executing each mutated version of the entire program. We also propose a multi-pass test generation system to further reduce runtime complexity and compact test data. We compare our tools with one of the best software test generation tools (EvoSuite[20], which won the SBST 2017 tool competition) and demonstrate that our approach generates higher quality unit tests in a scalable manner and provides a compact set of tests.","PeriodicalId":303560,"journal":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114835527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-23DOI: 10.1109/VTS.2019.8758635
Ahmed M. Y. Ibrahim, H. Kerkhoff, Abrar A. Ibrahim, M. Safar, M. El-Kharashi
The IEEE 1687 standard introduced a large design space of compliant networks for accessing embedded instruments. Such networks could grow in their structural complexity and inter-component temporal dependencies. Scan pattern retargeting is defined as the procedure of translating an instrument-level pattern to several network-level ones. Pattern retargeting could become computationally intensive with the increase of structural and temporal dependencies. Structured pattern retargeting was previously introduced as a formal and light-weight pattern retargeting methodology for arbitrary IEEE 1687 networks. In this work, we present a dedicated structured retargeting method for hierarchical IEEE 1687 networks. The proposed method significantly reduces the retargeting time for pure hierarchical networks compared to the general one, while resulting in the same network access time. The retargeting time is of a special importance in the case of on-chip retargeting, which is used for on-line monitoring using IEEE 1687 networks.
{"title":"Efficient Structured Scan Patterns Retargeting for Hierarchical IEEE 1687 Networks","authors":"Ahmed M. Y. Ibrahim, H. Kerkhoff, Abrar A. Ibrahim, M. Safar, M. El-Kharashi","doi":"10.1109/VTS.2019.8758635","DOIUrl":"https://doi.org/10.1109/VTS.2019.8758635","url":null,"abstract":"The IEEE 1687 standard introduced a large design space of compliant networks for accessing embedded instruments. Such networks could grow in their structural complexity and inter-component temporal dependencies. Scan pattern retargeting is defined as the procedure of translating an instrument-level pattern to several network-level ones. Pattern retargeting could become computationally intensive with the increase of structural and temporal dependencies. Structured pattern retargeting was previously introduced as a formal and light-weight pattern retargeting methodology for arbitrary IEEE 1687 networks. In this work, we present a dedicated structured retargeting method for hierarchical IEEE 1687 networks. The proposed method significantly reduces the retargeting time for pure hierarchical networks compared to the general one, while resulting in the same network access time. The retargeting time is of a special importance in the case of on-chip retargeting, which is used for on-line monitoring using IEEE 1687 networks.","PeriodicalId":303560,"journal":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130297138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-23DOI: 10.1109/VTS.2019.8758649
R. I. Bahar, Ulya R. Karpuzcu, Sasa Misailovic
Many important application domains, including machine learning, feature intrinsically noise tolerant algorithms. These algorithms process massive, yet noisy and redundant data, by probabilistic and often iterative techniques. As a result, there is a range of valid outputs rather than a single golden value. While this may translate into relaxed constraints for testing and verification of approximate systems, distinguishing actual design bugs from what is being approximated also becomes harder. In this paper, using representative case studies, we pose several challenges for the test and verification community as approximate computing becomes more prevalent as a design of choice in order to achieve performance gains, power or energy savings, improved reliability or reduced software and/or hardware complexity.
{"title":"Special Session: Does Approximation Make Testing Harder (or Easier)?","authors":"R. I. Bahar, Ulya R. Karpuzcu, Sasa Misailovic","doi":"10.1109/VTS.2019.8758649","DOIUrl":"https://doi.org/10.1109/VTS.2019.8758649","url":null,"abstract":"Many important application domains, including machine learning, feature intrinsically noise tolerant algorithms. These algorithms process massive, yet noisy and redundant data, by probabilistic and often iterative techniques. As a result, there is a range of valid outputs rather than a single golden value. While this may translate into relaxed constraints for testing and verification of approximate systems, distinguishing actual design bugs from what is being approximated also becomes harder. In this paper, using representative case studies, we pose several challenges for the test and verification community as approximate computing becomes more prevalent as a design of choice in order to achieve performance gains, power or energy savings, improved reliability or reduced software and/or hardware complexity.","PeriodicalId":303560,"journal":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125398531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Safety is one of the crucial features of autonomous drive platforms, and semiconductor chips used in these architectures must guarantee functional safety aspects mandated by ISO 26262 standard. To monitor the failures due to field defects, in-system-structural-tests are automatically run during key-on and/or key-off. Upon detection of any permanent defects by the in-system-test (IST) architecture, Drive platform responds to achieve the fail-safe state of the system. In this paper, we present the IST architecture that helps with achieving highest functional safety levels on the NVIDIA Drive platform.
{"title":"Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms","authors":"Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, S. Jiang","doi":"10.1109/VTS.2019.8758636","DOIUrl":"https://doi.org/10.1109/VTS.2019.8758636","url":null,"abstract":"Safety is one of the crucial features of autonomous drive platforms, and semiconductor chips used in these architectures must guarantee functional safety aspects mandated by ISO 26262 standard. To monitor the failures due to field defects, in-system-structural-tests are automatically run during key-on and/or key-off. Upon detection of any permanent defects by the in-system-test (IST) architecture, Drive platform responds to achieve the fail-safe state of the system. In this paper, we present the IST architecture that helps with achieving highest functional safety levels on the NVIDIA Drive platform.","PeriodicalId":303560,"journal":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126414790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-23DOI: 10.1109/VTS.2019.8758608
Abhishek Das, N. Touba
The IEEE Std. 1687 (IJTAG) was designed to provide on-chip access to the various embedded instruments (e.g. built-in self test, sensors, etc.) in complex system-on-chip designs. IJTAG facilitates access to on-chip instruments from third party intellectual property providers with hidden test-data registers. Although access to on-chip instruments provides valuable data specifically for debug and diagnosis, it can potentially expose the design to untrusted sources and instruments that can sniff and possibly manipulate the data that is being shifted through the IJTAG network. This paper provides a comprehensive protection scheme against data sniffing and data integrity attacks by selectively isolating the data flowing through the IJTAG network. The proposed scheme is modeled as a graph coloring problem to optimize the number of isolation signals required to protect the design. It is shown that combining the proposed approach with other existing schemes can also bolster the security against unauthorized user access as well. The proposed countermeasure is shown to add minimal overhead in terms of area and power consumption.
{"title":"A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation","authors":"Abhishek Das, N. Touba","doi":"10.1109/VTS.2019.8758608","DOIUrl":"https://doi.org/10.1109/VTS.2019.8758608","url":null,"abstract":"The IEEE Std. 1687 (IJTAG) was designed to provide on-chip access to the various embedded instruments (e.g. built-in self test, sensors, etc.) in complex system-on-chip designs. IJTAG facilitates access to on-chip instruments from third party intellectual property providers with hidden test-data registers. Although access to on-chip instruments provides valuable data specifically for debug and diagnosis, it can potentially expose the design to untrusted sources and instruments that can sniff and possibly manipulate the data that is being shifted through the IJTAG network. This paper provides a comprehensive protection scheme against data sniffing and data integrity attacks by selectively isolating the data flowing through the IJTAG network. The proposed scheme is modeled as a graph coloring problem to optimize the number of isolation signals required to protect the design. It is shown that combining the proposed approach with other existing schemes can also bolster the security against unauthorized user access as well. The proposed countermeasure is shown to add minimal overhead in terms of area and power consumption.","PeriodicalId":303560,"journal":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","volume":"13 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128488491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-23DOI: 10.1109/VTS.2019.8758667
A. Wahba, Li-C. Wang, Zheng Zhang, N. Sumikawa
In production test data analytics, it is often that an analysis involves the recognition of a conceptual pattern on a wafer map. A wafer pattern may hint a particular issue in the production by itself or guide the analysis into a certain direction. In this work, we introduce a novel approach to recognize patterns on a wafer map of pass/fail locations. Our approach utilizes Tucker decomposition to find projection matrices that are able to project a wafer pattern represented by a small set of training samples into a nearly-diagonal matrix. Properties of such a matrix are utilized to recognize wafers with a similar pattern. Also included in our approach is a novel method to select the wafer samples that are more suitable to be used together to represent a conceptual pattern in view of the proposed approach.
{"title":"Wafer Pattern Recognition Using Tucker Decomposition","authors":"A. Wahba, Li-C. Wang, Zheng Zhang, N. Sumikawa","doi":"10.1109/VTS.2019.8758667","DOIUrl":"https://doi.org/10.1109/VTS.2019.8758667","url":null,"abstract":"In production test data analytics, it is often that an analysis involves the recognition of a conceptual pattern on a wafer map. A wafer pattern may hint a particular issue in the production by itself or guide the analysis into a certain direction. In this work, we introduce a novel approach to recognize patterns on a wafer map of pass/fail locations. Our approach utilizes Tucker decomposition to find projection matrices that are able to project a wafer pattern represented by a small set of training samples into a nearly-diagonal matrix. Properties of such a matrix are utilized to recognize wafers with a similar pattern. Also included in our approach is a novel method to select the wafer samples that are more suitable to be used together to represent a conceptual pattern in view of the proposed approach.","PeriodicalId":303560,"journal":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126879789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-23DOI: 10.1109/VTS.2019.8758629
J. Rearick, A. Crouch, Hans Martin von Staudt
The IEEE 1687–2014 standard introduced the concept of portable, retargetable tests for digital circuits and taught how to apply them via a JTAG Test Access Port. Two follow-on standardization efforts address the topics of portable, retargetable analog tests (IEEE P1687.2) and applying analog or digital tests via non-TAP interfaces (IEEE P1687.1). IEEE P2427 complements these efforts by defining how to measure and report coverage of analog tests. This session will use a running example to show how all three initiatives play together.
{"title":"Innovative Practices on IEEE 1687.xyz","authors":"J. Rearick, A. Crouch, Hans Martin von Staudt","doi":"10.1109/VTS.2019.8758629","DOIUrl":"https://doi.org/10.1109/VTS.2019.8758629","url":null,"abstract":"The IEEE 1687–2014 standard introduced the concept of portable, retargetable tests for digital circuits and taught how to apply them via a JTAG Test Access Port. Two follow-on standardization efforts address the topics of portable, retargetable analog tests (IEEE P1687.2) and applying analog or digital tests via non-TAP interfaces (IEEE P1687.1). IEEE P2427 complements these efforts by defining how to measure and report coverage of analog tests. This session will use a running example to show how all three initiatives play together.","PeriodicalId":303560,"journal":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123619600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-23DOI: 10.1109/VTS.2019.8758598
M. Shulaker, L. Lebrun, B. Kaminska, B. Courtois
Continuing a tradition at the IEEE VLSI Test Symposium this new topic session presents two interesting talks on new emerging computing and testing techniques. The first talk focuses on carbon nanotube electronics while the second talk discusses about wafer level testing under magnetic field.
{"title":"Special Session (New Topic): Emerging Computing and Testing Techniques","authors":"M. Shulaker, L. Lebrun, B. Kaminska, B. Courtois","doi":"10.1109/VTS.2019.8758598","DOIUrl":"https://doi.org/10.1109/VTS.2019.8758598","url":null,"abstract":"Continuing a tradition at the IEEE VLSI Test Symposium this new topic session presents two interesting talks on new emerging computing and testing techniques. The first talk focuses on carbon nanotube electronics while the second talk discusses about wafer level testing under magnetic field.","PeriodicalId":303560,"journal":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116207078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-23DOI: 10.1109/VTS.2019.8758651
Ben Niewenhuis, B. Ravikumar, Z. Liu, R. D. Blanton
Previous work on the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) has achieved optimal testability for static fault models. This work explores enhancements to the CM- LCV that make delay faults optimally testable, with specific focus on the path delay fault model. Results from a design experiment indicate that the modified CM-LCV can achieve up to 100% robust path delay fault coverage, a significant improvement on the estimated 55.22% fault coverage for the reference benchmark design.
{"title":"Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle","authors":"Ben Niewenhuis, B. Ravikumar, Z. Liu, R. D. Blanton","doi":"10.1109/VTS.2019.8758651","DOIUrl":"https://doi.org/10.1109/VTS.2019.8758651","url":null,"abstract":"Previous work on the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) has achieved optimal testability for static fault models. This work explores enhancements to the CM- LCV that make delay faults optimally testable, with specific focus on the path delay fault model. Results from a design experiment indicate that the modified CM-LCV can achieve up to 100% robust path delay fault coverage, a significant improvement on the estimated 55.22% fault coverage for the reference benchmark design.","PeriodicalId":303560,"journal":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114637613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-23DOI: 10.1109/VTS.2019.8758662
Jubayer Mahmod, S. Millican, Ujjwal Guin, V. Agrawal
This article presents a brief survey of digital delay fault testing, which lists 100+ references on fault models, simulators, ATPG, DFT, and tools. Continuing studies are needed in this maturing field for new technologies, signal integrity, process variations, faster than critical path operation, asynchronous circuits, counterfeit ICs, and hardware Trojans. This information is compiled to provide direction to students, practicing engineers, and researchers alike.
{"title":"Special Session: Delay Fault Testing - Present and Future","authors":"Jubayer Mahmod, S. Millican, Ujjwal Guin, V. Agrawal","doi":"10.1109/VTS.2019.8758662","DOIUrl":"https://doi.org/10.1109/VTS.2019.8758662","url":null,"abstract":"This article presents a brief survey of digital delay fault testing, which lists 100+ references on fault models, simulators, ATPG, DFT, and tools. Continuing studies are needed in this maturing field for new technologies, signal integrity, process variations, faster than critical path operation, asynchronous circuits, counterfeit ICs, and hardware Trojans. This information is compiled to provide direction to students, practicing engineers, and researchers alike.","PeriodicalId":303560,"journal":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130551101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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