Reduction of packet order performance penalty in IBWR switches

Abstract

Packet order in slotted input buffer wavelength routed (IBWR) switches, operating under (i) synchronous optical packet switching (OPS), (ii) scattered wavelength path (SCWP) operational mode and (iii) fixed packet size, can be preserved by using a parallel iterative scheduler, as discussed in reference [1]. The performance achieved is comparable to the ideal output buffering architecture, degrading only for high input loads. The scheduler in [1] maintains packet order among every input fiber-output fiber pair. In virtual circuit-based networks, packet order has to be maintained among packets in the same traffic connection. Maintaining packet sequence among all packets in the same input fiber-output fiber pair is a constraint excessively hard. However, it is commonly used to simplify the scheduler design. This paper studies the performance improvement obtained in the OI-PDBM scheduler, if the ordering constrained is softened, and applied only among packets belonging to the same traffic connection. A GMPLS (generalized multiprotocol label switching) control plane is assumed, so that packet flow is identified by tagging information stored in packet header. A discussion regarding switch scheduler feasibility is also included.