Comparison of TDC parameters in 65 nm and 0.13 μm CMOS

Abstract

In this paper parameters of time to digital converter (TDC), which is often used as phase detector in all-digital frequency synthesizers, designed in 65 nm and 0.13 μm CMOS integrated circuit technologies, were analyzed. The structure of the designed TDC is a variety of 2D Vernier time to digital converter, based on gated ring oscillators. Performance of these oscillators has biggest impact on resolution of TDC. Therefore, oscillators were simulated using analog approach using Cadence integrated circuit design software. Simulations were carried out in nominal (1.2 V, 40 °C, typical transistor models), worst (1.1 V, 40 °C, slow transistor models) and best (1.3 V, −40 °C, fast transistor models) operation conditions. In the nominal operation conditions, the frequency of gated ring oscillator can be tuned from 0.68 GHz to 3.38 GHz and from 0.33 GHz to 0.71 GHz respectively in 65 nm and 0.13 μm technology. The delay of single stage can be changed from 491 ps to 98 ps and from 1.013 ns to 0.466 ns respectively in 65 nm and 0.13 μm CMOS. At least 3 and 5 sections of oscillator need to be enabled respectively in 65 nm and 0.13 μm CMOS for oscillator to start. Tuning step of oscillator's stage delay, which corresponds to resolution of TDC, in nominal operating conditions can be changed from 3.4 ps to 0.8 ps and from 5.8 ps to 1.1 ps respectively in 65 nm and 0.13 μm CMOS, when number of enabled oscillator's sections is changed from 20 to 48. Total area of silicon occupied by TDC is 123 μm × 148.8 μm in 65 nm CMOS technology and 244.2 μm × 295.8 μm in 0.13 μm CMOS technology.