A 1Gbit SDRAM With An Independent Sub-array Controlled Scheme And A Hierarchical Decoding Scheme

Abstract

A s the realm of high performance DRAM has been extended up to the Gigabit scale [1 ,2 ] , the large device size has been the major concern, presenting challenges in attaining acceptable yield and power consumption. A s the ratio of the total chip s ize and the minimum feature s ize is rapidly increased, even the smallest defects will cause failures, often very difficult t o analyze. Moreover, with high speed synchronous bank interleaving operation, the power consumption is large, requring a tight control of the power budget in the peripheral regions. Th i s paper presents design techniques utilizing the i n d e p e n d e n t sub-array controlled scheme and the hierarchical decoding scheme t o achieve enhanced failure analysis, lower power consumption, and smaller chip size in a prototype lGbit synchronous DRAM (SDRAM).