{"title":"A low-noise CMOS interface ASIC for capacitive MEMS accelerometer","authors":"Ying Wang, S. Gao, L. Shao, Yuntao Liu","doi":"10.1109/MEC.2011.6025495","DOIUrl":null,"url":null,"abstract":"A low noise interface application-specific integrated circuit (ASIC) for capacitive accelerometer is presented in this paper. A low-noise low-offset charge integrator is proposed to improve performance of the system. Correlated double sampling, closed-loop operational mode and PID controller are employed in this circuit to minimize the noise, offset and improve stability of the system. Meanwhile, by adding self-test circuit, it improves the reliability of the system. The AISC is fabricated in 0.5μm two-poly two-metal CMOS process, it operates under ± 5V supply with a power dissipation of 40mW. The tested results have shown that the noise floor of the accelerometer is 9.8μg/Hz1/2, the sensitivity is 1.32V/g, nonlinearity is 0.06% and the bias stability is 0.129mg.","PeriodicalId":386083,"journal":{"name":"2011 International Conference on Mechatronic Science, Electric Engineering and Computer (MEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Conference on Mechatronic Science, Electric Engineering and Computer (MEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MEC.2011.6025495","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A low noise interface application-specific integrated circuit (ASIC) for capacitive accelerometer is presented in this paper. A low-noise low-offset charge integrator is proposed to improve performance of the system. Correlated double sampling, closed-loop operational mode and PID controller are employed in this circuit to minimize the noise, offset and improve stability of the system. Meanwhile, by adding self-test circuit, it improves the reliability of the system. The AISC is fabricated in 0.5μm two-poly two-metal CMOS process, it operates under ± 5V supply with a power dissipation of 40mW. The tested results have shown that the noise floor of the accelerometer is 9.8μg/Hz1/2, the sensitivity is 1.32V/g, nonlinearity is 0.06% and the bias stability is 0.129mg.
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