{"title":"Parallel execution of the saturated reductions","authors":"B. Dinechin, Christophe Monat, F. Rastello","doi":"10.1109/SIPS.2001.957365","DOIUrl":null,"url":null,"abstract":"This paper addresses the problem of improving the execution performance of saturated reduction loops on fixed-point instruction-level parallel digital signal processors (DSPs). We first introduce \"bit-exact\" transformations, that are suitable for use in the ETSI and the ITU speech coding applications. We then present \"approximate\" transformations, the relative precision of which we are able to compare. Our main results rely on the properties of the saturated arithmetic.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"382 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2001.957365","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This paper addresses the problem of improving the execution performance of saturated reduction loops on fixed-point instruction-level parallel digital signal processors (DSPs). We first introduce "bit-exact" transformations, that are suitable for use in the ETSI and the ITU speech coding applications. We then present "approximate" transformations, the relative precision of which we are able to compare. Our main results rely on the properties of the saturated arithmetic.
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