Review of Different Flip-Flop Circuits and a Modified Flip-Flop Circuit for Low Voltage Operation

Abstract

In this paper, a less complex and single-phase clock flip-flop has been proposed. This flip-flop design is a modified version of the Novel Low-Complexity and Low-Power flip-flop. In the design of this flip-flop, a master-slave logic structure is used, representing a hybrid logic design consisting of both past transistor logic (PTL) and complementary metal-oxide-semiconductor (CMOS) logic. The proposed design comprises 15 transistors, two transistors less than the Low-complexity and low power flip-flop. The transistor reduction in this flip-flop is achieved by applying a logic structure reduction technique which also improves the power and timing performance of the design. The proposed plan is implemented on the 90 nm CMOS technology. The proposed plan is implemented on the 90 nm CMOS technology in Cadence Virtuoso tool. It is 48.13%, 30.94% and 22.71% of power saved as compared to TGFF, TCFF and LCLPFF respectively at 1 Volt power supply.