A Power Reduction Method for Scan Testing in Ultra-Low Power Designs

Abstract

In recent years, low power devices have become widely designed. Since the power supply design is based on the user operation, there is the possibility that it can malfunction in conventional scan testing on account of the excessive power consumption during scan testing. In order to overcome this problem, we have combined and adopted various scan testing techniques. This paper presents a scan testing approach that is demonstrated to be effective for ultra-low power devices. It splits one scan shift clock into several scan shift clocks per clock domain. Moreover, it changes the scan shift clock speed to cope with the inrush current. These clock controls are made possible by our own test clock controller.