Parametric mapping of neural networks to fine-grained FPGAs

Abstract

Steady FPGA density and speed improvement in recent years has paved the path for realization of larger Neural Networks On a Programmable Chip (NNOPC), a high performance and low cost alternative to traditional physical implementations of artificial neural networks. In this paper, we propose a parametric approach for mapping artificial neural networks onto FPGA structures, as well as an optimization method to reduce area requirements of the synthesized hardware. Applying this method to a sample neuron, we achieved a 30% reduction in hardware resource requirements of the synaptic multiplier.