Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227059
A. Korotkov, M. V. Telenkov
The paper presents a software tool for the analysis of oversampled switched-capacitor delta-sigma modulator as a main part of high-resolution A/D converters - delta-sigma ADC. Two hierarchical levels have been considered for modulator simulation: idealized behavioral level and non-ideal circuit level. The program is written in MATLAB and allows the most relevant non-ideal parameters of the components to be taken into account. Among these parameters are limited switch resistances and gain-bandwidth product of active devices. Simulation of pattern and idle noises are considered as well.
{"title":"Numerical simulation of oversampled switched-capacitor circuits","authors":"A. Korotkov, M. V. Telenkov","doi":"10.1109/SCS.2003.1227059","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227059","url":null,"abstract":"The paper presents a software tool for the analysis of oversampled switched-capacitor delta-sigma modulator as a main part of high-resolution A/D converters - delta-sigma ADC. Two hierarchical levels have been considered for modulator simulation: idealized behavioral level and non-ideal circuit level. The program is written in MATLAB and allows the most relevant non-ideal parameters of the components to be taken into account. Among these parameters are limited switch resistances and gain-bandwidth product of active devices. Simulation of pattern and idle noises are considered as well.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123125810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226955
S. Birca-Galateanu
Full-wave rectifiers allow to halves the dipole peak voltages or currents compared to half-wave ones. These values may still be high. Still class E resonant full-wave rectifier, analyzed now when driven by a square-wave voltage generator, has the peak diode current equal to the load current. Diode voltage slopes are ideally zero after switch off, for duty factors larger than 0.5. The circuit contains two rectifier diodes but a single LC circuit. Major parasitic inductances and capacitances are included in the rectifier topology.
{"title":"Low peak current class E resonant full-wave low dv/dt rectifier driven by a square-wave voltage generator","authors":"S. Birca-Galateanu","doi":"10.1109/SCS.2003.1226955","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226955","url":null,"abstract":"Full-wave rectifiers allow to halves the dipole peak voltages or currents compared to half-wave ones. These values may still be high. Still class E resonant full-wave rectifier, analyzed now when driven by a square-wave voltage generator, has the peak diode current equal to the load current. Diode voltage slopes are ideally zero after switch off, for duty factors larger than 0.5. The circuit contains two rectifier diodes but a single LC circuit. Major parasitic inductances and capacitances are included in the rectifier topology.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116985865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226952
E. Hjalmarson, R. Hagglund, L. Wanhammar
An efficient approach and an associated tool to optimize the performance of integrated analog circuits were described. The main objectives with the approach are to significantly speed up the design process and to obtain better overall, possibly optimal, circuit performance compared to a manual, simulation-based, approach. In order to achieve good agreement with circuit simulators high accuracy transistor models are used. A key feature is the automatic generation of the performance metrics and cost function from the circuit netlist. As a design example we select a current-mirror operational transconductance amplifier.
{"title":"An equation-based optimization approach for analog circuit design","authors":"E. Hjalmarson, R. Hagglund, L. Wanhammar","doi":"10.1109/SCS.2003.1226952","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226952","url":null,"abstract":"An efficient approach and an associated tool to optimize the performance of integrated analog circuits were described. The main objectives with the approach are to significantly speed up the design process and to obtain better overall, possibly optimal, circuit performance compared to a manual, simulation-based, approach. In order to achieve good agreement with circuit simulators high accuracy transistor models are used. A key feature is the automatic generation of the performance metrics and cost function from the circuit netlist. As a design example we select a current-mirror operational transconductance amplifier.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125505627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227017
M. Antoniu, L. Dimitriu, E. Antoniu, N. Thirer
The paper presents a speedometer using a capacitive sensor. It uses a ratiometric measurement electronic circuit, feature that allows eliminating the effect of activation voltage variations. The prototype, with digital display, allows the rotational speed measurement in the range of 2,000 to 20,000 rpm, with an accuracy better than 1.5% full range.
{"title":"A capacitive speedometer","authors":"M. Antoniu, L. Dimitriu, E. Antoniu, N. Thirer","doi":"10.1109/SCS.2003.1227017","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227017","url":null,"abstract":"The paper presents a speedometer using a capacitive sensor. It uses a ratiometric measurement electronic circuit, feature that allows eliminating the effect of activation voltage variations. The prototype, with digital display, allows the rotational speed measurement in the range of 2,000 to 20,000 rpm, with an accuracy better than 1.5% full range.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126632260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226963
D. Zito, L. Fanucci, B. Neri, S. Pascoli, G. Scandurra
This paper presents the design and post-layout simulation results for a single chip 1.8 GHz band-pass LNA using the boot-strapped inductor approach. It is characterized by a bandwidth of 54 MHz, a minimum noise figure of 1.8 dB, a transducer power gain of 27.5 dB, an input linearity range up to -20 dBm and a power consumption of 20.7 mW. The circuit features a proper self-adaptive compensation to achieve robustness against temperature variations.
{"title":"Single chip 1.8 GHz band pass LNA with temperature self-compensation","authors":"D. Zito, L. Fanucci, B. Neri, S. Pascoli, G. Scandurra","doi":"10.1109/SCS.2003.1226963","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226963","url":null,"abstract":"This paper presents the design and post-layout simulation results for a single chip 1.8 GHz band-pass LNA using the boot-strapped inductor approach. It is characterized by a bandwidth of 54 MHz, a minimum noise figure of 1.8 dB, a transducer power gain of 27.5 dB, an input linearity range up to -20 dBm and a power consumption of 20.7 mW. The circuit features a proper self-adaptive compensation to achieve robustness against temperature variations.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126851917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1226935
A. Dmitriev, A. Panas, S. Starkov
We consider high rate wireless communication scheme, based on wideband chaotic carrier, generated directly in microwave frequency band. Main features and the performances of proposed scheme are discussed. The experimental model of the system is designed and series of the experiments, demonstrating the wireless transmission with the data rates up to 200 Mbps are carried out.
{"title":"Communications with ultrawideband chaotic carrier","authors":"A. Dmitriev, A. Panas, S. Starkov","doi":"10.1109/SCS.2003.1226935","DOIUrl":"https://doi.org/10.1109/SCS.2003.1226935","url":null,"abstract":"We consider high rate wireless communication scheme, based on wideband chaotic carrier, generated directly in microwave frequency band. Main features and the performances of proposed scheme are discussed. The experimental model of the system is designed and series of the experiments, demonstrating the wireless transmission with the data rates up to 200 Mbps are carried out.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126806368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227094
M. Taherzadeh‐Sani, R. Lotfi, H. Zare-Hoseini, O. Shoaei
The power consumption is the most important issue in the design of integrated circuits for mobile electronics. In this paper a new approach employing a current injection transistor to the output stage in order to inject the additional current needed for the large-signal settling in that interval and off in the remaining small-signal regime is presented. This technique decreases the power consumption in a fast-settling high-slew-rate operational amplifier driving a large capacitive load. Using this technique, a 1.8-V 3.3-mW op-amp driving a 4-pF load is designed with a 2Vp-p,diff 12-bit settling time of less than 11ns in a 0.35-μm CMOS process. HSPICE simulations confirm that this approach can reduce the power consumption by considerable amounts as high as 50%.
在移动电子产品的集成电路设计中，功耗是最重要的问题。本文提出了一种在输出级采用电流注入晶体管的新方法，以便在该间隔注入大信号沉降所需的额外电流，并在剩余的小信号区关闭。该技术降低了驱动大容性负载的快速稳定高回转速率运算放大器的功耗。利用该技术，在0.35 μm CMOS工艺中设计了驱动4-pF负载的1.8 v 3.3 mw运放，其2Vp-p、diff 12位沉降时间小于11ns。HSPICE模拟证实，这种方法可以减少大量的功耗，高达50%。
{"title":"A high slew-rate low-voltage low-power operational amplifier using a new current injection circuit","authors":"M. Taherzadeh‐Sani, R. Lotfi, H. Zare-Hoseini, O. Shoaei","doi":"10.1109/SCS.2003.1227094","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227094","url":null,"abstract":"The power consumption is the most important issue in the design of integrated circuits for mobile electronics. In this paper a new approach employing a current injection transistor to the output stage in order to inject the additional current needed for the large-signal settling in that interval and off in the remaining small-signal regime is presented. This technique decreases the power consumption in a fast-settling high-slew-rate operational amplifier driving a large capacitive load. Using this technique, a 1.8-V 3.3-mW op-amp driving a 4-pF load is designed with a 2Vp-p,diff 12-bit settling time of less than 11ns in a 0.35-μm CMOS process. HSPICE simulations confirm that this approach can reduce the power consumption by considerable amounts as high as 50%.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123371348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227093
S. Minaei, C. Temizyurek
A new first-order dual-input all-pass filter in current-mode operation using the differential voltage current conveyor (DVCC) is proposed. The novelty of the configuration is that the DVCC supplies high input impedances for applications requesting differential or floating inputs. PSPICE simulation results verifying theoretical analyses are also included.
{"title":"Dual input all-pass filter using DVCC","authors":"S. Minaei, C. Temizyurek","doi":"10.1109/SCS.2003.1227093","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227093","url":null,"abstract":"A new first-order dual-input all-pass filter in current-mode operation using the differential voltage current conveyor (DVCC) is proposed. The novelty of the configuration is that the DVCC supplies high input impedances for applications requesting differential or floating inputs. PSPICE simulation results verifying theoretical analyses are also included.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121146320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227102
L. Stoica
In the present paper, the transient performance of correlated input data is studied for LMS adaptive algorithm. Analysis is performed for adaptive systems identification with stationary Gaussian inputs. The LMS adaptive algorithm behavior is tested in a system identification application using Matlab simulations.
{"title":"Transient performance degradation of the LMS adaptive algorithm","authors":"L. Stoica","doi":"10.1109/SCS.2003.1227102","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227102","url":null,"abstract":"In the present paper, the transient performance of correlated input data is studied for LMS adaptive algorithm. Analysis is performed for adaptive systems identification with stationary Gaussian inputs. The LMS adaptive algorithm behavior is tested in a system identification application using Matlab simulations.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121201618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-10DOI: 10.1109/SCS.2003.1227126
A. Burian, J. Takala
The detection type problems represent a special case of nonlinear mapping. This fact makes the use of neural networks attractive for signal detection problems. In order to obtain good generalization excessive tuning is needed. Also, most of the neural network learning theories does not make use of the optimal hyperplane concept. In this paper, we consider optimal hyperplane signal detection with support vector machines (SVMs), for detecting a known signal corrupted by noise. Experimental results illustrate the detection performances in various cases. The practical implementation and the robustness of SVMs are also considered.
{"title":"On signal detection using support vector machines","authors":"A. Burian, J. Takala","doi":"10.1109/SCS.2003.1227126","DOIUrl":"https://doi.org/10.1109/SCS.2003.1227126","url":null,"abstract":"The detection type problems represent a special case of nonlinear mapping. This fact makes the use of neural networks attractive for signal detection problems. In order to obtain good generalization excessive tuning is needed. Also, most of the neural network learning theories does not make use of the optimal hyperplane concept. In this paper, we consider optimal hyperplane signal detection with support vector machines (SVMs), for detecting a known signal corrupted by noise. Experimental results illustrate the detection performances in various cases. The practical implementation and the robustness of SVMs are also considered.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121658463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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