SOC Design Challenges in a Multi-threaded 65nm Dual Core Xeon® MP Processor

Abstract

A multi-threaded dual-core Xeonreg MP processor with 16 MB of L3 cache and operating at a top frequency of 3.4 GHz has been developed using a non-traditional SOC design methodology on a 65 nm process technology. The design methodology embodied highly controlled, customized, and high impact changes to the underlying pre-existing processor cores resulting in performance and functionality that approaches a fully custom design while maintaining high re-use of the existing processor core. This paper presents the key design methodologies and the challenges.