A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures

Abstract

In this paper, we propose a built-in self-diagnosis (BISD) mechanism for delay faults induced by degradation. This mechanism solely generates expected signatures using slower clock on the fly and requires no memory for storing pre-computed expected signatures. In our experiment, the proposed BISD mechanism is applied to benchmark circuits. Area overhead and diagnostic resolution are evaluated.