Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.000-5
Manobendra Nath Mondal, A. B. Chowdhury, Manjari Pradhan, S. Sur-Kolay, B. Bhattacharya
Most of the Automatic Test Pattern Generation (ATPG) algorithms for digital circuits rely heavily on netlist description that comprises both network interconnect structure among logic gates and the functionality of each gate. The performance of an ATPG tool on a circuit-under-test (CUT) C is determined by the size of the test set T and its fault coverage (FC). Despite extensive research in the field of testing, the following question remains unanswered: Is the structure or the functionality of C dominant in determining FC of a test-set T for C? In this paper, we present empirical evidence in favour of the dominance of structure on FC by randomly selecting a logic gate from a synthesized netlist for C, and replacing it by a different type of gate. Our experiments provide an un-intuitive result that F C of a test-set T for C under the single stuck-at fault model remains nearly the same on other sibling circuits that have identical structure as of C but with different gate functionality, provided these have similar extent of fault redundancy. This observation supports the view that feeding structural information alone may suffice to train machine-learning models that are currently being used to expedite different problems of digital circuit testing and diagnosis.
{"title":"Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test","authors":"Manobendra Nath Mondal, A. B. Chowdhury, Manjari Pradhan, S. Sur-Kolay, B. Bhattacharya","doi":"10.1109/ATS47505.2019.000-5","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.000-5","url":null,"abstract":"Most of the Automatic Test Pattern Generation (ATPG) algorithms for digital circuits rely heavily on netlist description that comprises both network interconnect structure among logic gates and the functionality of each gate. The performance of an ATPG tool on a circuit-under-test (CUT) C is determined by the size of the test set T and its fault coverage (FC). Despite extensive research in the field of testing, the following question remains unanswered: Is the structure or the functionality of C dominant in determining FC of a test-set T for C? In this paper, we present empirical evidence in favour of the dominance of structure on FC by randomly selecting a logic gate from a synthesized netlist for C, and replacing it by a different type of gate. Our experiments provide an un-intuitive result that F C of a test-set T for C under the single stuck-at fault model remains nearly the same on other sibling circuits that have identical structure as of C but with different gate functionality, provided these have similar extent of fault redundancy. This observation supports the view that feeding structural information alone may suffice to train machine-learning models that are currently being used to expedite different problems of digital circuit testing and diagnosis.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122627210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00018
Hau Sim Choo, C. Y. Ooi, M. Inoue, N. Ismail, M. Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok, F. Hussin
Hardware Trojan refers to a malicious modification of an integrated circuit (IC). To eliminate the complications arising from designing an IC which includes a Trojan, it is suggested to apply Trojan detection as early as at register-transfer level (RTL). In this paper, we propose a hardware Trojan detection framework which consists of both RTL and gate-level classification using machine learning approaches to detect hardware Trojan inserted at RTL. In the experiment, all Trojan benchmarks were successfully identified without false positive detection on non-Trojan benchmark.
{"title":"Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level","authors":"Hau Sim Choo, C. Y. Ooi, M. Inoue, N. Ismail, M. Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok, F. Hussin","doi":"10.1109/ATS47505.2019.00018","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00018","url":null,"abstract":"Hardware Trojan refers to a malicious modification of an integrated circuit (IC). To eliminate the complications arising from designing an IC which includes a Trojan, it is suggested to apply Trojan detection as early as at register-transfer level (RTL). In this paper, we propose a hardware Trojan detection framework which consists of both RTL and gate-level classification using machine learning approaches to detect hardware Trojan inserted at RTL. In the experiment, all Trojan benchmarks were successfully identified without false positive detection on non-Trojan benchmark.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129205676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00020
Chee Hoo Kok, C. Y. Ooi, M. Inoue, M. Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, N. Ismail, F. Hussin
As integrated chip (IC) is one of the most essential components for communication devices, enhancing the integrity of hardware security is essential to prevent any security breach. Implantation of Hardware Trojan (HT) into the IC is one of the most threatening hardware security risks since most of the IC design and fabrication phases are outsourced to third-party foundries. Gate-level netlist inspection is utterly important as HT could be easily hidden among the primitives of the circuit which makes the detection challenging. Previously, HT detection methods for gate-level netlist were mainly based on either net testability or net's structural features. In this paper, we proposed to consolidate these two types of features into a single feature vector to train supervised machine learning classifiers. We also analyzed the performance of the classifiers based on different combinations of features using Minimum Redundancy and Maximum Relevance (mRMR) technique. Using the best feature combination, we achieved a 99.85% True Positive Rate (TPR), 99.95% True Negative Rate (TNR) and 99.90% accuracy (ACC). The results were validated using 10-fold cross-validation.
{"title":"Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection","authors":"Chee Hoo Kok, C. Y. Ooi, M. Inoue, M. Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, N. Ismail, F. Hussin","doi":"10.1109/ATS47505.2019.00020","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00020","url":null,"abstract":"As integrated chip (IC) is one of the most essential components for communication devices, enhancing the integrity of hardware security is essential to prevent any security breach. Implantation of Hardware Trojan (HT) into the IC is one of the most threatening hardware security risks since most of the IC design and fabrication phases are outsourced to third-party foundries. Gate-level netlist inspection is utterly important as HT could be easily hidden among the primitives of the circuit which makes the detection challenging. Previously, HT detection methods for gate-level netlist were mainly based on either net testability or net's structural features. In this paper, we proposed to consolidate these two types of features into a single feature vector to train supervised machine learning classifiers. We also analyzed the performance of the classifiers based on different combinations of features using Minimum Redundancy and Maximum Relevance (mRMR) technique. Using the best feature combination, we achieved a 99.85% True Positive Rate (TPR), 99.95% True Negative Rate (TNR) and 99.90% accuracy (ACC). The results were validated using 10-fold cross-validation.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130426348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00015
Vinay B. Y. Kumar, S. Deb, Rupesh Kumar, Mustafa Khairallah, A. Chattopadhyay, A. Mendelson
The growing threat of various attacks on modern microprocessors and systems calls for major design overhauls ranging from plugging micro-architectural side channels such as due to speculative execution to implementing cryptographic accelerators for side-channel and fault attack resistance. In this paper, we suggest to focus on the similarities and the differences between fault tolerance techniques and countermeasures against attacks on security sensitive systems. Modern digital circuits and systems use a diverse set of techniques to ensure operational correctness in the presence of faults. From a security perspective, the goal is to ensure a set of stated security properties hold in the presence of 'security faults' (extending the notion of conventional faults to include injected faults as well as vulnerabilities such as passive side-channels). A point of note here is that under some security faults, the operational correctness may not be compromised. This paper advocates the re-purposing of some of the known fault tolerance techniques, and show how those can be useful for enhancing security in the presence of active side-channel attacks. As a simple illustration of these ideas, we present an experimental case study in fortifying a cryptographic sub-component of a RISC-V based secure system-on-chip, against a formidable fault attack called SIFA.
{"title":"Recruiting Fault Tolerance Techniques for Microprocessor Security","authors":"Vinay B. Y. Kumar, S. Deb, Rupesh Kumar, Mustafa Khairallah, A. Chattopadhyay, A. Mendelson","doi":"10.1109/ATS47505.2019.00015","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00015","url":null,"abstract":"The growing threat of various attacks on modern microprocessors and systems calls for major design overhauls ranging from plugging micro-architectural side channels such as due to speculative execution to implementing cryptographic accelerators for side-channel and fault attack resistance. In this paper, we suggest to focus on the similarities and the differences between fault tolerance techniques and countermeasures against attacks on security sensitive systems. Modern digital circuits and systems use a diverse set of techniques to ensure operational correctness in the presence of faults. From a security perspective, the goal is to ensure a set of stated security properties hold in the presence of 'security faults' (extending the notion of conventional faults to include injected faults as well as vulnerabilities such as passive side-channels). A point of note here is that under some security faults, the operational correctness may not be compromised. This paper advocates the re-purposing of some of the known fault tolerance techniques, and show how those can be useful for enhancing security in the presence of active side-channel attacks. As a simple illustration of these ideas, we present an experimental case study in fortifying a cryptographic sub-component of a RISC-V based secure system-on-chip, against a formidable fault attack called SIFA.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114567161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00025
Sayandeep Sanyal, A. Patra, P. Dasgupta, M. Bhattacharya
The traditional body of literature on analog testing deals with propagation of faults to the output nets of the circuit. Often the set of detectable faults remains unsatisfactory because suitable stimuli cannot be found for propagating certain faults to the output. Existing technology supports capturing of the state of internal nets of a circuit, thereby enhancing the scope of detecting faults by observing their effect on internal nets. This approach is feasible only if the number of internal nets probed by the built-in test structure is very few. This paper presents a structured approach that identifies the sensitive nets, namely a well chosen small subset of internal nets that are affected by these faults. We utilize the speed of DC analysis and some common behavioral aspects of analog signals to find out this subset. We report dramatic improvement in fault coverage on several circuits including benchmarks.
{"title":"A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits","authors":"Sayandeep Sanyal, A. Patra, P. Dasgupta, M. Bhattacharya","doi":"10.1109/ATS47505.2019.00025","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00025","url":null,"abstract":"The traditional body of literature on analog testing deals with propagation of faults to the output nets of the circuit. Often the set of detectable faults remains unsatisfactory because suitable stimuli cannot be found for propagating certain faults to the output. Existing technology supports capturing of the state of internal nets of a circuit, thereby enhancing the scope of detecting faults by observing their effect on internal nets. This approach is feasible only if the number of internal nets probed by the built-in test structure is very few. This paper presents a structured approach that identifies the sensitive nets, namely a well chosen small subset of internal nets that are affected by these faults. We utilize the speed of DC analysis and some common behavioral aspects of analog signals to find out this subset. We report dramatic improvement in fault coverage on several circuits including benchmarks.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124107606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00028
Arighna Deb, D. K. Das
Quantum circuits have recently been developed thanks to the global companies like IBM, Google, Microsoft and Intel. The physical realization of quantum circuits motivates to explore new areas of research. Testing of quantum circuits is one such area which needs significant attention in order to detect faulty gate operations in the circuits. To this end, first we need to identify the different types of faults that can result due to some unwanted physical failures during the implementation of the gate operations. This paper investigates those possibilities of physical failures in realizing the quantum operations and introduces a new family of fault models for quantum circuits. Experimental results include the actual number of newly proposed faults that can occur at the physical level of any quantum circuit.
{"title":"Detailed Fault Model for Physical Quantum Circuits","authors":"Arighna Deb, D. K. Das","doi":"10.1109/ATS47505.2019.00028","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00028","url":null,"abstract":"Quantum circuits have recently been developed thanks to the global companies like IBM, Google, Microsoft and Intel. The physical realization of quantum circuits motivates to explore new areas of research. Testing of quantum circuits is one such area which needs significant attention in order to detect faulty gate operations in the circuits. To this end, first we need to identify the different types of faults that can result due to some unwanted physical failures during the implementation of the gate operations. This paper investigates those possibilities of physical failures in realizing the quantum operations and introduces a new family of fault models for quantum circuits. Experimental results include the actual number of newly proposed faults that can occur at the physical level of any quantum circuit.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131325966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ats47505.2019.00-22
{"title":"Message from the ATS 2019 Program Co-Chairs","authors":"","doi":"10.1109/ats47505.2019.00-22","DOIUrl":"https://doi.org/10.1109/ats47505.2019.00-22","url":null,"abstract":"","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"AES-16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126540665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00021
Renjie Lu, Haihua Shen, Yu Su, Huawei Li, Xiaowei Li
Hardware Trojan (HT) has paid more and more attention to the academia and industry because of its significant potential threat. In this paper, we propose a novel approach, named GramsDet, to detect HT through capturing suspicious circuit connection structure using recurrent neural network. GramsDet considers that HT usually be inserted into the regions with low transition probability, so the circuit fragments associated with HT should have special connection structures. GramsDet models the target circuit using n-gram circuit segmentation technique, and implements the "gate embedding" by the order-sensitive co-occurrence matrix. Then, a stacked long short-term memory network is designed to build a robust HT detection model. The experimental results on different benchmarks show that GramsDet can detect effectively Trojan logic without the "Golden model" of the circuit under detection (CUD).
{"title":"GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network","authors":"Renjie Lu, Haihua Shen, Yu Su, Huawei Li, Xiaowei Li","doi":"10.1109/ATS47505.2019.00021","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00021","url":null,"abstract":"Hardware Trojan (HT) has paid more and more attention to the academia and industry because of its significant potential threat. In this paper, we propose a novel approach, named GramsDet, to detect HT through capturing suspicious circuit connection structure using recurrent neural network. GramsDet considers that HT usually be inserted into the regions with low transition probability, so the circuit fragments associated with HT should have special connection structures. GramsDet models the target circuit using n-gram circuit segmentation technique, and implements the \"gate embedding\" by the order-sensitive co-occurrence matrix. Then, a stacked long short-term memory network is designed to build a robust HT detection model. The experimental results on different benchmarks show that GramsDet can detect effectively Trojan logic without the \"Golden model\" of the circuit under detection (CUD).","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116754592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.000-2
Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, P. Girard, X. Wen
To meet the requirements of both cost-effectiveness and high reliability for safety-critical terrestrial applications, this paper proposes a novel radiation hardened latch design, namely HLCRT. The HLCRT latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has correct values on its output node, i.e., the latch is effectively DNU hardened. Simulation results demonstrate the DNU tolerance of the proposed latch. Moreover, due to the use of fewer transistors, clock gating technologies, and a high-speed path, the proposed latch saves about 444.80% delay, 150.50% power, 72.66% area, and 2029.63% delay-power-area product on average, compared with state-of-the-art DNU hardened latch designs.
{"title":"Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications","authors":"Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, P. Girard, X. Wen","doi":"10.1109/ATS47505.2019.000-2","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.000-2","url":null,"abstract":"To meet the requirements of both cost-effectiveness and high reliability for safety-critical terrestrial applications, this paper proposes a novel radiation hardened latch design, namely HLCRT. The HLCRT latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has correct values on its output node, i.e., the latch is effectively DNU hardened. Simulation results demonstrate the DNU tolerance of the proposed latch. Moreover, due to the use of fewer transistors, clock gating technologies, and a high-speed path, the proposed latch saves about 444.80% delay, 150.50% power, 72.66% area, and 2029.63% delay-power-area product on average, compared with state-of-the-art DNU hardened latch designs.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"361 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122762396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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