Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits

Abstract

As the complexity of the digital circuits increases there should be a check on its functionality in a more exhaustive way. So here comes the need for test pattern generation technique to detect the presence of the faults and to obtain the test patterns. The switching activity in digital circuits may overheat the circuit due to which unwanted responses may occur. This may lead to a high power consumption, so it is necessary to reduce the power. The proposed paper includes generation of test patterns and a technique for test power reduction in VLSI. The results have been validated using ISCAS’85 and ISCAS’89 benchmark circuits.