Design of low noise high speed novel dynamic Analog Comparator in 65nm technology

Abstract

Analog Comparator is designed to compare two analog inputs and outputs a logical signal indicating which of the inputs is greater or lesser. Comparators, being an essential building block of most high speed devices like Analogue to Digital Converters, are one of the most important components used in signal processing and communication systems. Also it plays a challenging role in high speed mixed signal system designs. In this paper, we have presented an ultra-high speed simple dynamic comparator design using 65nm UMC technology. The circuit is operating at a clock frequency of 6.66GHz and input signal frequency of around 3.33GHz. The propagation delay is minimized to about 47.14ps with a low noise of about 0.531fV2/Hz which makes the proposed structure favourable for Flash or Pipelined data conversion applications. However, it uses only a total of 12 MOS transistors with minimum W/L ratios to make the circuit simple and area efficient, without affecting its performance. With the enhancement of speed and keeping other parameters like power & energy at its optimum value, this comparator circuit is a novel design that can be used in any high speed applications.