Luís Duarte, Luís Rodrigues, L. N. Alves, Carlos Ribeiro, M. Figueiredo
{"title":"DLL architecture for OFDM based VLC transceivers in FPGA","authors":"Luís Duarte, Luís Rodrigues, L. N. Alves, Carlos Ribeiro, M. Figueiredo","doi":"10.1109/CSNDSP.2016.7573949","DOIUrl":null,"url":null,"abstract":"This paper addresses the problem of achieving high bandwidth in a DLL design for OFDM based VLC broadcast systems. It describes the implementation of efficient Data Link Layer (DLL) and Forward Error Correction (FEC) modules in a Xilinx FPGA. The proposed DLL aims at furnishing the adequate means to fragment and route both high data-rate (HDR) and moderate data-rate (MDR) service requests while maintaining a continuous transmission flow. The FEC modules aims at providing sufficient error correction capabilities with reasonable computation overheads. Another goal was to develop these modules under a globally asynchronous locally synchronous paradigm, ensuring high modularity and performance.","PeriodicalId":298711,"journal":{"name":"2016 10th International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 10th International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSNDSP.2016.7573949","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper addresses the problem of achieving high bandwidth in a DLL design for OFDM based VLC broadcast systems. It describes the implementation of efficient Data Link Layer (DLL) and Forward Error Correction (FEC) modules in a Xilinx FPGA. The proposed DLL aims at furnishing the adequate means to fragment and route both high data-rate (HDR) and moderate data-rate (MDR) service requests while maintaining a continuous transmission flow. The FEC modules aims at providing sufficient error correction capabilities with reasonable computation overheads. Another goal was to develop these modules under a globally asynchronous locally synchronous paradigm, ensuring high modularity and performance.