Slew rate and delay optimization of sense amplifier using tradeoff between supply voltage and threshold

Abstract

Output of SRAM memory circuit is very small i.e. in few milli volts. While reading logic 1 sometimes it is read as logic 0. Due to this malfunctioning of circuit, problem of hazards occur. To overcome this problem we use sense amplifiers. The work of sense amplifier is to sense low power signal from bit line of SRAM memory circuit and amplify the small voltage swing to recognizable logic levels so that data can be interpreted clearly by logic outside the memory. Here we have reduced the delay of the sense amplifier by optimizing the supply voltage i.e. VDD. For this purpose tradeoff between delays, VDD and offset voltage has been done. We have examined the results using IC flow tool.