The evolution of interconnect management in physical synthesis

Prashant Saxena
{"title":"The evolution of interconnect management in physical synthesis","authors":"Prashant Saxena","doi":"10.1109/VDAT.2009.5158086","DOIUrl":null,"url":null,"abstract":"With the worsening of interconnects due to scaling, the reliance of the original physical synthesis paradigm on merely some placement of the cells in order to predict net delays no longer suffices. Practitioners have augmented this paradigm over the years with increasingly sophisticated net models in an effort to improve the accuracy of the interconnect delay predictions. In this paper, we will review these advances and motivate their natural evolution towards “guaranteed” net delays by describing a new scheme known as persistence. Although a naïve implementation of persistence can result in unroutable circuits, we will describe how persistence can be applied intelligently in an industrial flow to improve the circuit optimization without impacting its congestion.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2009.5158086","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

With the worsening of interconnects due to scaling, the reliance of the original physical synthesis paradigm on merely some placement of the cells in order to predict net delays no longer suffices. Practitioners have augmented this paradigm over the years with increasingly sophisticated net models in an effort to improve the accuracy of the interconnect delay predictions. In this paper, we will review these advances and motivate their natural evolution towards “guaranteed” net delays by describing a new scheme known as persistence. Although a naïve implementation of persistence can result in unroutable circuits, we will describe how persistence can be applied intelligently in an industrial flow to improve the circuit optimization without impacting its congestion.
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物理综合互连管理的演变
随着互连的恶化,由于规模,原来的物理合成范式的依赖仅仅是一些放置的细胞,以预测净延迟不再足够。多年来,为了提高互连延迟预测的准确性,从业人员已经用越来越复杂的网络模型增强了这一范式。在本文中,我们将回顾这些进展,并通过描述一种称为持久性的新方案来激励它们向“保证”净延迟的自然进化。虽然持久性的naïve实现可能导致不可路由的电路,但我们将描述如何在工业流中智能地应用持久性来改进电路优化而不影响其拥塞。
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