Optimization of test time and fault grading of functional test vectors using fault simulation flow

Abstract

Structural test is the most efficient test to detect manufacturing defects. With ever increasing complexity of digital designs, structural test vectors alone are not sufficient to achieve the desired fault coverage. Functional test vectors are programs written with the design specifications in mind rather than manufacturing defects and this can help in testing some of the critical portions of design. Functional test vectors are given by the functional verification team. Structural and Functional tests put together can increase the Test quality very significantly. Unlike structural test vectors, functional test vectors do not offer test coverage metric on their own. In this paper, comparative analysis between conventional ATPG method and fault grading using fault simulation flow is done on I2C design. Fault grading technique is implemented using ATPG and Fault simulation flow to fault grade the functional test vectors. This greatly reduces the test vectors which indeed reduces test time and test effort.