Structural fault collapsing by superposition of BDDs for test generation in digital circuits

Abstract

The paper presents a new structural fault-independent fault collapsing method based on the topology analysis of the circuit, which has linear complexity. The minimal necessary set of faults as the target objective for test generation is found. The main idea is to produce fault collapsing concurrently with the construction of structurally synthesized binary decision diagrams (SSBDD) used for test generation, as a side effect. To improve the fault collapsing, a new class of BDDs in a form of SSBDDs with multiple inputs (SSMIBDD) is proposed, which allows a significant reduction of the model complexity for test generation purposes, and produces collapsed fault sets with less sizes than the SSBDDs provide. Experimental data show that the fault collapsing by the proposed method is considerably more efficient than other structural fault collapsing methods with comparative time cost. The method is especially efficient for circuits with high rate of internal fanouts.