Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator

Abstract

This paper presents an all-digital 1st-order 1-bit $\Delta \Sigma $ time-to-digital converter (TDC). A single-step integration method is proposed to perform differential time integration using a bi-directional gated delay line (BDGDL) to reduce integration time. An in-depth investigation into the impact of process uncertainty on the TDC is provided. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM4 device models. The simulation results of the TDC with a 244 kHz sinusoidal input of amplitude 333 ps over frequency range from flicker noise corner frequency to 3rd-order harmonic frequency demonstrate that the TDC provides SNDR of 39.8 dB and time resolution of 4.2 ps while consuming 396.6 μW. The figure-of-merit (FOM) of the TDC is 3.6 pJ/step, better that of reported TDCs alike. The effect of process uncertainty on the TDC can be minimized by tuning the delay blocks of the TDC.