M. Fujita, Takeshi Matsumoto, A. M. Gharehbaghi, Kosuke Oshima, Satoshi Jo, Hiroaki Yoshida, Takashi Takenaka, K. Wakabayashi
{"title":"Formal Verification and Debugging of VLSI Logic Design for Systems Dependability: Experiments and Evaluation","authors":"M. Fujita, Takeshi Matsumoto, A. M. Gharehbaghi, Kosuke Oshima, Satoshi Jo, Hiroaki Yoshida, Takashi Takenaka, K. Wakabayashi","doi":"10.1007/978-4-431-56594-9_14","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":127041,"journal":{"name":"VLSI Design and Test for Systems Dependability","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design and Test for Systems Dependability","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-4-431-56594-9_14","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}