IP design of a reconfigurable baseline JPEG coding

Hao-Chieh Chang, Li-Lin Chen, Chung-Jr Lian, Yung-Chi Chang, Liang-Gee Chen
{"title":"IP design of a reconfigurable baseline JPEG coding","authors":"Hao-Chieh Chang, Li-Lin Chen, Chung-Jr Lian, Yung-Chi Chang, Liang-Gee Chen","doi":"10.1109/APASIC.1999.824048","DOIUrl":null,"url":null,"abstract":"IP design of a complete, reconfigurable baseline JPEG encoder is presented in this paper. It features completely JFIF (JPEG File Interchange Format) compatible bit-stream output and a user-defined quantization table that can be re-configured at the run time and the compiling time. Thus, various hardware configurations can be easily achieved. Besides, modularized design is practiced such that smooth data flow in this pipelined architecture can be easily achieved by utilizing a central controller. This technique improves system performance greatly.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824048","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

IP design of a complete, reconfigurable baseline JPEG encoder is presented in this paper. It features completely JFIF (JPEG File Interchange Format) compatible bit-stream output and a user-defined quantization table that can be re-configured at the run time and the compiling time. Thus, various hardware configurations can be easily achieved. Besides, modularized design is practiced such that smooth data flow in this pipelined architecture can be easily achieved by utilizing a central controller. This technique improves system performance greatly.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
一种可重构基线JPEG编码的IP设计
本文提出了一个完整的、可重构的基线JPEG编码器的IP设计。它具有完全兼容JFIF (JPEG文件交换格式)的比特流输出和用户定义的量化表,可以在运行时和编译时重新配置。因此,可以很容易地实现各种硬件配置。此外,采用模块化设计,通过使用中央控制器,可以轻松实现流水线架构中的平滑数据流。这种技术大大提高了系统性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A 50% power reduction scheme for CMOS relaxation oscillator Design and analysis of symmetric dual-layer spiral inductors for RF integrated circuits Implementation of a cycle-based simulator for the design of a processor core A high-performance low-power asynchronous matrix-vector multiplier for discrete cosine transform A 120 MHz SC 4th-order elliptic interpolation filter with accurate gain and offset compensation for direct digital frequency synthesizer
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1